M41T82RM6F STMicroelectronics, M41T82RM6F Datasheet - Page 43

• Manufacturer Part Number: M41T82RM6F
• Description: IC RTC SERIAL W/BATT SW 8-SOIC
• Manufacturer: STMicroelectronics
• Type: Clock/Calendar/Alarmr

Specifications of M41T82RM6F

• Memory Size: 32B
• Time Format: HH:MM:SS:hh (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8279-2; M41T82RM6F

M41T82-M41T83
3.14.2
Table 16.
1. OUT is bit 7 of register 08h (digital calibration).
2. ABE is bit 5 of register 0Ah (alarm 1, month).
3. A1IE is bit 7 of register 0Ah (alarm 1, month).
4. OFIE is bit 7 of register 09h (watchdog).
OUT
x
1
0
1
(1)
Backup mode
In backup mode, the operation of the output circuit is as shown in
Priority for IRQ1/FT/OUT pin when operating in backup mode
In backup mode, frequency test is disabled. Thus, the FT bit is a ‘don’t care’.
ABE enables interrupts in backup. If it is 0, the output pin is a 1 regardless of the other bits.
The pin is also a 1 when OUT is a 1 and no interrupts are enabled.
When OUT is 0 and ABE is a 1, the pin is 0 regardless of the interrupts.
Thus, in order to enable interrupts in backup mode, OUT must be a 1 and ABE must be a 1,
and one or more of the interrupt enables must be a 1.
Simultaneous interrupts
Since more than one interrupt source can cause the IRQ1/FT/OUT pin to go low, more than
one interrupt may be pending when the microprocessor services the interrupt. Therefore,
the application software should read the flags register (0Fh) to discern which condition or
conditions are causing the pin to be asserted.
Also be aware that once a flag causes the pin to assert, other flags could subsequently also
go true. Since the pin is already low due to the first, no additional output transition will occur.
That is why the software must check the flags register.
Example: If the watchdog is in use and the oscillator fail detect interrupt is enabled, and the
watchdog times out, the IRQ1/FT/OUT pin will go low. If, in the intervening time before the
processor services the interrupt, something disturbs the oscillator, such as a drop of
moisture landing on the crystal pins, the OF bit will also be set. Thus, when the software
services the interrupt, it must service both sources: it must re-initialize the watchdog and
clear the OF bit in order to de-assert the IRQ1/FT/OUT pin. By reading the flags register, the
software will know both flags were set and that both need service.
ABE
0
1
1
x
(2)
+ OFIE
A1IE
0
1
x
x
(3)
(4)
Doc ID 12578 Rev 12
IRQ
Pin
1
1
0
When ABE is 0, the pin is 1 regardless of OUT or
the interrupt sources.
When OUT is 1 and no interrupts are enabled,
the pin is 1. (A1IE and OFIE are the only
interrupts applicable in this mode).
When ABE is 1 and OUT is 0, OUT dominates
and regardless of the interrupt sources.
When one or more interrupts are enabled, ABE is
a 1, and OUT is a 1, the pin stays high until one of
the interrupts is asserted.
Comment
Table
16.
Clock operation
43/61