M41T56M6E STMicroelectronics, M41T56M6E Datasheet - Page 10

• Manufacturer Part Number: M41T56M6E
• Description: IC SRAM SRL TIMEKPR 512BIT 8SOIC
• Manufacturer: STMicroelectronics
• Type: Clock/Calendar/NVSRAMr

Specifications of M41T56M6E

• Memory Size: 56B
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Function: Clock/Calendar
• Rtc Memory Size: 64 Byte
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Rtc Bus Interface: Serial (2-Wire, I2C)
• Nvram Features: RTC, Internal Battery, XTAL
• Interface Type: I2C, Serial, 2-Wire
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-2818-5; M41T56M6

M41T56
Figure 12. Alternative READ Mode Sequence
WRITE Mode
In this mode the master transmitter transmits to
the M41T56 slave receiver. Bus protocol is shown
in
dition and slave address, a logic '0' (R/W = 0) is
placed on the bus and indicates to the addressed
device that word address A
written to the on-chip address pointer. The data
word to be written to the memory is strobed in next
and the internal address pointer is incremented to
the next memory location within the RAM on the
reception of an acknowledge clock. The M41T56
slave receiver will send an acknowledge clock to
the master transmitter after it has received the
slave address and again after it has received the
word address and each data byte (see Figure 10).
Figure 13. WRITE Mode Sequence
10/24
Figure 13., page
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
10. Following the START con-
S
S
ADDRESS
n
SLAVE
ADDRESS
will follow and is to be
SLAVE
ADDRESS (n)
WORD
DATA n
Data Retention Mode
With valid V
cessed as described above with READ or WRITE
cycles. Should the supply voltage decay, the
M41T56 will automatically deselect, write protect-
ing itself when V
V
hibiting access to the clock registers and SRAM.
When V
Switchover Voltage (V
from the V
isters and SRAM are maintained from the attached
battery supply.
All outputs become high impedance. On power up,
when V
tion continues for t
For a further more detailed review of battery life-
time calculations, please see Application Note
AN1012.
DATA n
DATA n+1
PFD
(min). This is accomplished by internally in-
CC
CC
CC
returns to a nominal value, write protec-
DATA n+1
CC
falls below the Battery Back-up
pin to the battery and the clock reg-
applied, the M41T56 can be ac-
CC
REC
falls between V
SO
.
), power input is switched
DATA n+X
DATA n+X
AI00895
AI00591
PFD
P
P
(max) and