LTC2440IGN#TRPBF Linear Technology, LTC2440IGN#TRPBF Datasheet - Page 18

• Manufacturer Part Number: LTC2440IGN#TRPBF
• Description: IC ADC DIFFER 24-BIT HS 16-SSOP
• Manufacturer: Linear Technology

Specifications of LTC2440IGN#TRPBF

• Number Of Bits: 24
• Sampling Rate (per Second): 3.5k
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 40mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LTC2440
APPLICATIONS INFORMATION
on this fi rst rising edge of SCK and concludes after the
32nd rising edge. Data is shifted out the SDO pin on each
falling edge of SCK. The internally generated serial clock
is output to the SCK pin. This signal may be used to shift
the conversion result into external circuitry. EOC can be
latched on the fi rst rising edge of SCK and the last bit of
the conversion result on the 32nd rising edge of SCK.
After the 32nd rising edge, SDO goes HIGH (EOC = 1),
SCK stays HIGH and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pull-
ing CS HIGH anytime between the fi rst and 32nd rising
edge of SCK, see Figure 9. In order to properly select the
OSR for the conversion following a data abort, fi ve SCK
rising edges must be seen prior to performing a data out
abort (pulling CS HIGH). If CS is pulled high prior to the
fi fth SCK falling edge, the OSR selected depends on the
number of SCK signals seen prior to data abort, where
subsequent nonaborted conversion cycles return to the
programmed OSR. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
18
(INTERNAL)
BUSY
SDO
SCK
CS
Hi-Z
SLEEP
>t
EOCtest
1
BIT 0
EOC
5
CONVERSION
Hi-Z
DATA OUTPUT
TEST EOC
Figure 9. Internal Serial Clock, Reduced Data Output Length
Hi-Z
TEST EOC
ANALOG INPUT RANGE
REFERENCE VOLTAGE
SLEEP
–0.5V
Hi-Z
<t
REF
EOCtest
0.1V TO V
TO 0.5V
BIT 31
EOC
1μF
4.5V TO 5.5V
REF
CC
1, 8, 9, 16
BIT 30
2
3
4
5
6
V
REF
REF
IN
IN
GND
CC
+
–
LTC2440
+
–
new conversion. This is useful for systems not requiring
all 32-bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 10. CS may be permanently tied to ground, sim-
plifying the user interface or isolation barrier. The internal
serial clock mode is selected by tying EXT HIGH.
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1) and BUSY = 1. Once the
conversion is complete, SCK, BUSY and SDO go LOW (EOC
= 0) indicating the conversion has fi nished and the device
has entered the low power sleep state. The part remains in
the sleep state a minimum amount of time (≈500ns) then
immediately begins outputting data. The data output cycle
begins on the fi rst rising edge of SCK and ends after the
32nd rising edge. Data is shifted out the SDO pin on each
BIT 29
SIG
BUSY
SDO
SCK
EXT
SDI
CS
f
O
15
14
13
12
11
10
7
DATA OUTPUT
BIT 28
MSB
V
CC
3-WIRE
SPI INTERFACE
V
BIT 27
CC
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
200nV NOISE, 50/60Hz REJECTION
10-SPEED/RESOLUTION PROGRAMMABLE
2μV NOISE, 880Hz OUTPUT RATE
BIT 26
BIT 8
CONVERSION
Hi-Z
TEST EOC
2440 F09
2440fd