CS5014-BL14Z Cirrus Logic Inc, CS5014-BL14Z Datasheet - Page 13

• Manufacturer Part Number: CS5014-BL14Z
• Description: IC ADC 14BIT SELF-CALBR 44-PLCC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5014-BL14Z

• Number Of Bits: 14
• Sampling Rate (per Second): 56k
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 250mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1075-5

All calibration, conversion, and throughput times
directly scale to CLKIN frequency. Thus,
throughput can be precisely controlled and/or
maximized using an external CLKIN signal. In
contrast, the CS5012A/14/16’s internal oscillator
will vary from unit-to-unit and over temperature.
The CS5012A/14/16 can typically convert with
CLKIN as low as 10 kHz at room temperature.
Initiating Conversions
A falling transition on the HOLD pin places the
input in the hold mode and initiates a conversion
cycle. Upon completion of the conversion cycle,
the CS5012A/14/16 automatically return to the
track mode. In contrast to systems with separate
track-and-holds and A/D converters, a sampling
clock can simply be connected to the HOLD in-
put (Figure 3a). The duty cycle of this clock is
not critical. It need only remain low at least one
CLKIN cycle plus 50 ns, but no longer than the
minimum conversion time or an additional con-
version cycle will be initiated with inadequate
time for acquisition.
Microprocessor-Controlled Operation
Sampling and conversion can be placed under
microprocessor control (Figure 4) by simply gat-
ing the devices’ decoded address with the write
strobe for the HOLD input. Thus, a write cycle to
the CS5012A/14/16’s base address will initiate a
conversion. However, the write cycle must be to
DS14F8
DS14F9
Figure 4a. Conversions Asynchronous to CLKIN
Address
ADDR VALID
Bus
CONCLK
A2
A1
A0
RD
AN
A3
Addr
Dec
INTRLV
CAL
A0
RD
HOLD
CS
CS5012A/14/16
the odd address (A0 high) to avoid initiating a
software controlled reset (see Reset below).
The calibration control inputs, CAL, and
INTRLV are inputs to a set of transparent latches.
These signals are internally latched by CS return-
ing high. They must be in the appropriate state
whenever the chip is selected during a read or
write cycle. Address lines A1 and A2 are shown
connected to CAL and INTRLV in Figure 4 plac-
ing calibration under microprocessor control as
well. Thus, any read or write cycle to the
CS5012A/14/16’s base address will initiate or ter-
minate calibration. Alternatively, A0, INTRLV,
and CAL may be connected to the microproces-
sor data bus.
Conversion Time/Throughput
Upon completing a conversion cycle and return-
ing to the track mode, the CS5012A/14/16
require time to acquire the analog input signal
before another conversion can be initiated. The
acquisition time is specified as six CLKIN cycles
plus 2.25
only). This adds to the conversion time to define
the converter’s maximum throughput. The con-
version time of the CS5012A/14/16, in turn,
depends on the sampling, calibration, and CLKIN
conditions.
Figure 4b. Conversions under Microprocessor Control
Address
Bus
ADDR VALID
CS5012A CS5014 CS5016
AN
A3
µ
s (1.32
WR
RD
A2
A1
A0
CS5012A, CS5014, CS5016
Dec
Addr
µ
s for the CS5012A -7 version
A0
RD
CS
HOLD
CAL
INTRLV
CS5012A/14/16
2-19
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