CS5014-BL14Z Cirrus Logic Inc, CS5014-BL14Z Datasheet - Page 17

• Manufacturer Part Number: CS5014-BL14Z
• Description: IC ADC 14BIT SELF-CALBR 44-PLCC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5014-BL14Z

• Number Of Bits: 14
• Sampling Rate (per Second): 56k
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 250mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1075-5

To interface with a 16-bit data bus, the BW input
to the CS5012A/14/16 should be held high and
all data bits (12, 14 and 16 for the CS5012A,
CS5014 and CS5016 respectively) read in paral-
lel on pins D4-D15 (CS5012A), D2-D15
(CS5014), or D0-D15 (CS5016). With an 8-bit
bus, the converter’s result must be read in two
portions. In this instance, BW should be held low
and the 8 MSB’s obtained on the first read cycle
following a conversion. The second read cycle
will yield the remaining LSB’s (4, 6 or 8 for the
CS5012A/14/16 respectively) with 4, 2 or 0 trail-
ing zeros. Both bytes appear on pins D0-D7. The
upper/lower bytes of the same data will continue
to toggle on subsequent reads until the next con-
(A0=1)
DS14F8
DS14F9
Data
PIN
D0
D1
D2
D3
D4
D5
D6
D7
CS5012A
CS5012A
CS5014
CS5016
CS5014
CS5016
(A0=0)
Status
STATUS BIT
S0
S1
S2
S3
S4
S5
S6
S7
B11 B10
B13
B15
D15 D14 D13
X
X
X
X
"X" Denotes High Impedance Output
B12
B14
X
X
X
X
END OF CONVERSION
END OF TRACK
CONVERTING
CALIBRATING
RESERVED
LOW BYTE/HIGH BYTE
RESERVED
TRACKING
B9
B11
B13
STATUS
X
X
X
X
B8
B10
B12
D12 D11 D10
Figure 7. CS5012A/14/16 Data Format
X
X
X
X
Table 2. Status Pin Definitions
B7
B9
B11
X
X
X
X
B6
B8
B10
X
X
X
X
B5
B7
B9
D9
X
X
X
X
Falls upon completion of a conversion,
and returns high on the first subsequent read.
Reserved for factory use.
When data is to be read in an 8-bit format (BW=0),
indicates which byte will appear at the output next.
When low, indicates the input has been acquired to
the devices specified accuracy.
Reserved for factory use.
High when the device is tracking the input.
High when the device is converting the held input.
High when the device is calibrating.
B4
B6
B8
D8
X
X
X
X
version finishes. Status bit S2 indicates which
byte will appear on the next data read operation.
The CS5012A/14/16 internally buffer their output
data, so data can be read while the devices are
tracking or converting the next sample. Therefore,
retrieving the converters’ digital output requires
no reduction in ADC throughput. Enabling the 3-
state outputs while the CS5012A/14/16 is
converting will not introduce conversion errors.
Connecting CMOS logic to the digital outputs is
recommended.
DEFINITION
B11 B10
B3
B13 B12
B5
B15 B14
B7
B3
B5
B7
D7
S7
B2
B4
B6
B2
B4
B6
S6
D6
CS5012A CS5014 CS5016
B9
B1
B11
B3
B13
B5
B1
B3
B5
D5
S5
B8
B0
B10
B2
B12
B4
B0
B2
B4
S4
D4
CS5012A, CS5014, CS5016
B7
0
B9
B1
B11 B10
B3
S3
D3
0
B1
B3
B6
0
B8
B0
B2
S2
D2
0
B0
B2
B5
0
B7
0
B9
B1
D1
0
0
B1
S1
D0
0
0
B0
B4
0
B6
0
B8
B0
S0
16-Bit Bus
8- or 16-Bit
8-Bit Bus
Data Bus
(BW=1)
(BW=0)
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