CS5014-BL14Z Cirrus Logic Inc, CS5014-BL14Z Datasheet - Page 21

• Manufacturer Part Number: CS5014-BL14Z
• Description: IC ADC 14BIT SELF-CALBR 44-PLCC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5014-BL14Z

• Number Of Bits: 14
• Sampling Rate (per Second): 56k
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 250mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1075-5

obtain the specified accuracy. Figure 11 illustrates
this operation. During pre-charge the charge on
the capacitor array first settles to the buffered ver-
sion of the analog input. This voltage is offset
from the actual input voltage. During fine-charge,
the charge then settles to the accurate unbuffered
version.
The acquisition time of the CS5012A/14/16 de-
pends on the CLKIN frequency. This is due to a
fixed pre-charge period. For instance, operating
the CS5012A, CS5014, or CS5016
version with an external 4 MHz CLKIN results in
a 3.75
(6 clock cycles) and 2.25
Fine-charge settling is specified as a maximum of
2.25
than 200 Ω. (For the CS5012A
specified as 1.32
requires a source impedance of less than 400 Ω
around 2 MHz for stability, which is met by prac-
tically all bipolar op amps. Large dc source
impedances can be accommodated by adding ca-
pacitance from AIN to ground (typically 200 pF)
to decrease source impedance at high frequencies.
However, high dc source resistances will increase
the input’s RC time constant and extend the nec-
DS14F8
CS5012A/14/16
HOLD
Input
CS5012A/14/16
EOC
Output
MUX
Address
CS5012A/14/16
Analog
Input
DS14F9
µ
s for an analog source impedance of less
µ
s acquisition time: 1.5
Address N
µ
s.) In addition, the comparator
Convert Channel N
to Channel N + 1
µ
MUX Settling
s for fine-charging.
µ
s for pre-charging
Figure 12. Pipelined MUX Input Channels
Address N + 1
-7
version it is
-16
Convert Channel N+1
essary acquisition time. For more information on
input applications, consult the application note:
Input Buffer Amplifiers for the CS501X Family of
A/D Converters.
During the first six clock cycles following a con-
version (pre-charge) in unipolar mode, the
CS5012A is capable of slewing at 20V/
CS5014/16 can slew at 5V/µs. In bipolar mode,
only half the capacitor array is connected to the
analog input so the CS5012A can slew at 40V/
and the CS5014/16 can slew at 10V/µs. After the
first six CLKIN cycles, the CS5012A will slew at
1.25V/
mode, and the CS5014/16 will slew at 0.25V/µs
in unipolar mode and 0.5V/µs in bipolar mode.
Acquisition of fast slewing signals (step func-
tions) can be hastened if the step occurs during or
immediately following the conversion cycle. For
instance, channel selection in multiplexed appli-
cations should occur while the CS5012A/14/16 is
converting (see Figure 12). Multiplexer settling is
thereby removed from the overall throughput
equation, and the CS5012A/14/16 can convert at
full speed.
to Channel N + 2
MUX Settling
µ
s in unipolar mode and 3.0V/
CS5012A CS5014 CS5016
Address N + 2
CS5012A, CS5014, CS5016
Address N + 3
µ
s in bipolar
µ
s and the
2-27
µ
21
s,