PIC18F86K90-I/PT Microchip Technology, PIC18F86K90-I/PT Datasheet - Page 240

• Manufacturer Part Number: PIC18F86K90-I/PT
• Description: 64kB Flash, 4kB RAM, 1kB EE, 16MIPS, NanoWatt XLP, LCD, 5V 80 TQFP 12x12x1mm TRA
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F86K90-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87K90 FAMILY
18.1.2
When operating in Output mode (the Compare or PWM
modes), the drivers for the CCPx pins can be optionally
configured as open-drain outputs. This feature allows
the voltage level on the pin to be pulled to a higher level
through an external pull-up resistor and allows the
output to communicate with external circuits without the
need for additional level shifters.
The open-drain output option is controlled by the
CCPxOD bits (ODCON2<7:2>). Setting the appropriate
bit configures the pin for the corresponding module for
open-drain operation.
18.1.3
The pin assignment for CCP6/7/8/9 (Capture input,
Compare and PWM output) can change, based on the
device configuration.
The ECCPMX Configuration bit (CONFIG3H<1>)
determines the pin to which CCP6/7/8/9 is multiplexed.
The pin assignments for these CCP modules are given
in Table 18-4.
TABLE 18-4:
DS39957B-page 240
ECCPMX
(Default)
Value
1
0
OPEN-DRAIN OUTPUT OPTION
PIN ASSIGNMENT FOR CCP6,
CCP7, CCP8 AND CCP9
CCP6
RH7
RE6
CCP PIN ASSIGNMENT
CCP7
Pin Mapped To
RH6
RE5
CCP8
RH5
RE4
CC9
RH4
RE3
Preliminary
18.2
In Capture mode, the CCPR4H:CCPR4L register pair
captures the 16-bit value of the TMR1 or TMR3 register
when an event occurs on the CCP4 pins. An event is
defined as one of the following:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
The event is selected by the mode select bits,
CCP4M<3:0> (CCP4CON<3:0>). When a capture is
made, the interrupt request flag bit, CCP4IF (PIR4<1>),
is set. (It must be cleared in software.) If another
capture occurs before the value in CCPR4 is read, the
old captured value is overwritten by the new captured
value.
Figure 18-1 shows the Capture mode block diagram.
18.2.1
In Capture mode, the appropriate CCPx pin should be
configured as an input by setting the corresponding
TRIS direction bit.
18.2.2
For the available timers (1/3/5/7) to be used for the cap-
ture feature, the used timers must be running in Timer
mode or Synchronized Counter mode. In Asynchronous
Counter mode, the capture operation may not work.
The timer to be used with each CCP module is selected
in the CCPTMRSx registers. (See Section 18.1.1 “CCP
Modules and Timer Resources”.)
Details of the timer assignments for the CCP modules
are given in Table 18-2 and Table 18-3.
Note:
Capture Mode
CCP PIN CONFIGURATION
If RC1 or RE7 is configured as a CCP4
output, a write to the port causes a capture
condition.
TIMER1/3/5/7 MODE SELECTION
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