MT48LC8M32B2P-6 Micron Technology Inc, MT48LC8M32B2P-6 Datasheet - Page 32

• Manufacturer Part Number: MT48LC8M32B2P-6
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC8M32B2P-6

• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 17/7.5/5.5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 165mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
09005aef8140ad6d
MT48LC8M32B2_2.fm - Rev. B 10/04 EN
7. READs or WRITEs to bank m listed under Command (Action) include READs or WRITEs with auto precharge enabled and
8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when its burst has been interrupted
9. Burst in bank n continues as initiated.
READs or WRITEs with auto precharge disabled.
by bank m’s burst.
interrupt the READ on bank n, CAS latency later (Figure 9).
interrupt the READ on bank n when registered (Figures 12 and 13). DQM should be used one clock prior to the WRITE
command to prevent bus contention.
interrupt the WRITE on bank n when registered (Figure 20), with the data-out appearing CAS latency later. The last valid
WRITE to bank n will be data-in registered one clock prior to the READ to bank m.
will interrupt the WRITE on bank n when registered (Figure 18). The last valid WRITE to bank n will be data-in registered
one clock prior to the READ to bank m.
interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is reg-
istered (Figure 24).
interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent
bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 28).
interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to
bank n will begin after
bank n will be data-in registered one clock prior to the READ to bank m (Figure 29).
interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after
begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to
the WRITE to bank m (Figure 30).
t
WR is met, where
t
WR begins when the READ to bank m is registered. The last valid WRITE to
32
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©2003 Micron Technology, Inc. All rights reserved.
t
WR is met, where
256Mb: x32
SDRAM
t
WR