MT48LC8M32B2P-6 Micron Technology Inc, MT48LC8M32B2P-6 Datasheet - Page 9

• Manufacturer Part Number: MT48LC8M32B2P-6
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC8M32B2P-6

• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 17/7.5/5.5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 165mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Table 3:
09005aef8140ad6d
MT48LC8M32B2_2.fm - Rev. B 10/04 EN
M3, M2, P1, N2, R1,
N3, R2, E8, D7, D8,
G2, G3, H1, H2, J3,
R8, N7, R9, N8, P9,
B9, C8, A9, C7, A8,
A2, C3, A1, C2, B1,
E3, E7, H3, H7, K2,
G8, G9, F7, F3, G1,
B2, B7, C9, D9, E1,
B8, B3, C1, D1, E9,
L1, M9, N9, P2, P7
L9, M1, N1, P3, P8
90-BALL FBGA
M8, M7, L8, L2,
K9, K1, F8, F2
A7, F9, L7, R7
A3, F1, L3, R3
D2, D3, E2
J9, K7, K8
G7, H9
J7, H8
K3
J1
J2
J8
Ball Descriptions (FBGA)
RAS#, CAS#,
DQ0–DQ31
SYMBOL
BA0, BA1
DQM0-3
A0–A11
V
V
WE#
CKE
V
CLK
CS#
V
NC
DD
SS
DD
SS
Q
Q
Supply DQ Power: Provide isolated power to DQs for improved noise immunity.
Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.
Supply Power Supply: Voltage dependant on option.
Supply Ground.
TYPE
Input
Input
Input
Input
Input
Input
Input
I/O
–
Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF
REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in
any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is
synchronous except after the device enters power-down and self refresh
modes, where CKE becomes asynchronous until after exiting the same
mode. The input buffers, including CLK, are disabled during power-down
and self refresh modes, providing low standby power. CKE may be tied
HIGH.
Chip Select: CS# enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS# is registered
HIGH. CS# provides for external bank selection on systems with multiple
banks. CS# is considered part of the command code.
Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the
command being entered.
Input/Output Mask: DQM is sampled HIGH and is an input mask signal for
write accesses and an output enable signal for read accesses. Input data is
masked during a WRITE cycle. The output buffers are placed in a High-Z
state (two-clock latency) when during a READ cycle. DQM0 corresponds to
DQ0–DQ7; DQM1 corresponds to DQ8–DQ15; DQM2 corresponds to DQ16–
DQ23; and DQM3 corresponds to DQ24–DQ31. DQM0–DQM3 are
considered same state when referenced as DQM.
Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE, or PRECHARGE command is being applied. These balls also
provide the op-code during a LOAD MODE REGISTER command
Address Inputs: A0–A11 are sampled during the ACTIVE command (row-
address A0–A11) and READ/WRITE command (column address A0–A8; with
A10 defining auto precharge) to select one location out of the memory
array in the respective bank. A10 is sampled during a PRECHARGE
command to determine if all banks are to be precharged (A10 HIGH) or
bank selected by BA0, BA1 (LOW). The address inputs also provide the op-
code during a LOAD MODE REGISTER command.
Data Input/Output: Data bus.
No Connect: These pins should be left unconnected. H3 is a No Connect for
this part but may be used as A12 in future designs.
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
©2003 Micron Technology, Inc. All rights reserved.
256Mb: x32
SDRAM