MT46H16M32LFCM-75 Micron Technology Inc, MT46H16M32LFCM-75 Datasheet - Page 29

• Manufacturer Part Number: MT46H16M32LFCM-75
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H16M32LFCM-75

• Organization: 16Mx32
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 6.5/6ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 100mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

PDF: 09005aef82d5d305
512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN
10. Clock frequency is only permitted to change during clock stop, power-down, or self re-
11. In cases where the device is in self refresh mode for
12.
13. Referenced to each output group: for x16, LDQS with DQ[7:0]; and UDQS with DQ[15:8].
14. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/
15. The transition time for input signals (CAS#, CKE, CS#, DM, DQ, DQS, RAS#, WE#, and ad-
16. These parameters guarantee device timing but are not tested on each device.
17. The valid data window is derived by achieving other specifications:
18.
19.
20.
21. Fast command/address input slew rate ≥1 V/ns. Slow command/address input slew rate
22. The refresh period equals 64ms. This equates to an average refresh rate of 7.8125μs.
23. This is not a device limit. The device will operate with a negative value, but system per-
24. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command.
25. The maximum limit for this parameter is not a device limit. The device will operate with
26. At least 1 clock cycle is required during
27. Clock must be toggled a minimum of two times during the
8. CAS latency definition: with CL = 2, the first data element is valid at (
9. Timing tests may use a V
clock at which the READ command was registered; for CL = 3, the first data element is
valid at (2 ×
timing is still referenced to V
ing reference voltage level is V
fresh mode.
of the clock and ends when CKE transitions HIGH.
t
next highest integer.
For x32, DQS0 with DQ[7:0]; DQS1 with DQ[15:8]; DQS2 with DQ[23:16]; and DQS3 with
DQ[31:24].
DQS slew rate is less than 1.0 V/ns, timing must be derated: 50ps must be added to
and
tionality is uncertain.
dresses) are measured between V
V
and
duty cycle and a practical data valid window can be derived. The clock is allowed a maxi-
mum duty cycle variation of 45/55. Functionality is uncertain when operating beyond a
45/55 ratio.
t
CK# inputs, collectively.
t
These parameters are not referenced to a specific voltage level, but specify when the
device output is no longer driving (
t
≥0.5 V/ns. If the slew rate is less than 0.5 V/ns, timing must be derated:
tional 50ps per each 100 mV/ns reduction in slew rate from the 0.5 V/ns.
added, therefore, it remains constant. If the slew rate exceeds 4.5 V/ns, functionality is
uncertain.
formance could be degraded due to bus turnaround.
The case shown (DQS going from High-Z to logic low) applies when no WRITEs were pre-
viously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH
during this time, depending on
a greater value for this parameter, but system performance (bus turnaround) will de-
grade accordingly.
DAL = (
HP (MIN) is the lesser of
HZ and
HZ (MAX) will prevail over
IL(AC)
t
t
DH for each 100 mV/ns reduction in slew rate. If the slew rate exceeds 4 V/ns, func-
QH (
for falling input signals.
t
t
WR/
LZ transitions occur in the same access time windows as valid data transitions.
t
HP -
t
t
CK +
CK) + (
Electrical Specifications – AC Operating Conditions
t
QHS). The data valid window derates directly proportional with the clock
t
AC) after the first clock at which the READ command was registered.
t
RP/
t
CK): for each term, if not already an integer, round up to the
IL
t
CL (MIN) and
-to-V
29
t
DQSCK (MAX) +
DDQ
IH
DDQ
512Mb: x16, x32 Mobile LPDDR SDRAM
t
/2 or to the crossing point for CK/CK#. The output tim-
DQSS.
swing of up to 1.5V in the test environment, but input
IL(DC)
/2.
t
HZ) or begins driving (
Micron Technology, Inc. reserves the right to change products or specifications without notice.
to V
t
t
CH (MIN) actually applied to the device CK and
WR time when in auto precharge mode.
IH(AC)
t
RPST (MAX) condition.
for rising input signals and V
t
CKE,
t
t
CKE starts at the rising edge
LZ).
t
XSR period.
© 2004 Micron Technology, Inc. All rights reserved.
t
HP (
t
CK +
t
IS has an addi-
t
t
CK/2),
IH has 0ps
t
AC) after the
IH(DC)
t
DQSQ,
to
t
DS