MT9HTF6472FY-667D5E4 Micron Technology Inc, MT9HTF6472FY-667D5E4 Datasheet - Page 8

• Manufacturer Part Number: MT9HTF6472FY-667D5E4
• Manufacturer: Micron Technology Inc

Specifications of MT9HTF6472FY-667D5E4

• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 240FBDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 512Mb
• Package Type: FBDIMM
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 95C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / Rohs Status: Compliant

Table 8: Input DC Voltage and Operating Conditions
Table 9: Clock Rates
I
Table 10: I
PDF: 09005aef81a2f1eb
htf9c64_128x72fy.pdf - Rev. C 12/09 EN
Parameter
AMB supply voltage
DDR2 SDRAM supply voltage
Termination voltage
EEPROM supply voltage
SPD input high (logic 1) voltage
SPD input low (logic 0) voltage
RESET input high (logic 1) voltage
RESET input low (logic 0) voltage
Leakage current (RESET)
Leakage current (link)
Symbol
I
I
I
DD
DD_IDLE_0
DD_IDLE_1
DD_ACTIVE_1
FBDIMM Link Data Rate
Conditions and Specifications
3.2 Gb/s
4.0 Gb/s
4.8 Gb/s
DD
Conditions
Notes:
Note:
Condition
Idle current, single, or last DIMM: L0 state; Idle (0% bandwidth); Primary channel ena-
bled; Secondary channel disabled; CKE HIGH; Command and address lines stable; DDR2
SDRAM clock active
Idle current, first DIMM: L0 state; Idle (0% bandwidth); Primary and secondary channels
enabled; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active
Active power: L0 state; 50% DRAM bandwidth; 67% READ; 33% WRITE; Primary and secon-
dary channels enabled; DDR2 SDRAM clock active; CKE HIGH
3. See applicable DDR2 SDRAM component data sheet for
1. Applies to AMB and SPD.
2. Applies to serial memory buffer (SMB) and SPD bus signals.
3. Applies to AMB CMOS signal RESET#.
4. For all other AMB-related DC parameters, please refer to the high-speed differential link
1. DDR2 components may exceed the listed module speed grades; module may not be avail-
ter settings. The
ry to sustain <85°C operation.
interface specification.
able in all listed speed grades
Reference Clock
133 MHz
167 MHz
200 MHz
512MB, 1GB (x72, SR) 240-Pin DDR2 SDRAM FBDIMM
t
REFI parameter is used to specify the doubled refresh interval necessa-
Symbol
V
V
V
V
V
V
DDSPD
V
IH(DC)
IH(DC)
V
IL(DC)
IL(DC)
l
l
DD
CC
TT
L
L
8
0.48 × V
Min
1.46
–90
1.7
2.1
–5
DRAM Clock
3
–
1
–
Micron Technology, Inc. reserves the right to change products or specifications without notice.
266 MHz
333 MHz
400 MHz
DD
I
DD
Conditions and Specifications
0.5 × V
Nom
1.5
1.8
3.3
–
–
–
–
–
–
DD
t
REFI and extended mode regis-
0.52 × V
V
Max
1.54
DDSPD
+90
© 2005 Micron Technology, Inc. All rights reserved.
1.9
3.6
0.8
0.5
+5
–
DRAM Data Rate
DD
533 Mb/s
666 Mb/s
800 Mb/s
Units
µA
µA
V
V
V
V
V
V
V
V
Notes
1
2
2
3
2
3
4