MT9HTF6472FY-667D5E4 Micron Technology Inc, MT9HTF6472FY-667D5E4 Datasheet - Page 9

• Manufacturer Part Number: MT9HTF6472FY-667D5E4
• Manufacturer: Micron Technology Inc

Specifications of MT9HTF6472FY-667D5E4

• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 240FBDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 512Mb
• Package Type: FBDIMM
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 95C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / Rohs Status: Compliant

Table 10: I
Table 11: I
Table 12: I
Table 13: I
Table 14: I
PDF: 09005aef81a2f1eb
htf9c64_128x72fy.pdf - Rev. C 12/09 EN
Symbol
I
I
I
I
I
I
Total power
I
I
Total power
I
I
Total power
I
I
Total power
DD_ACTIVE_2
DD_TRAINING
DD_IBIST
DD_EI
CC
DD
CC
DD
CC
DD
CC
DD
Symbol
Symbol
Symbol
Symbol
DD
DD
DD
DD
DD
Conditions (Continued)
Specifications – 512MB DDR2-533
Specifications – 512MB DDR2-667
Specifications – 512MB DDR2-800
Specifications – 1GB DDR2-533
I
I
I
I
DD_IDLE_0
DD_IDLE_0
DD_IDLE_0
DD_IDLE_0
2200
1060
2600
1105
2200
1060
TBD
TBD
TBD
Note:
5.5
5.5
6.2
Condition
Active power, data pass through: L0 state; 50% DRAM bandwidth to downstream
DIMM; 67% READ; 33% WRITE; Primary and secondary channels enabled; DDR2 SDRAM
clock active; CKE HIGH; Command and address lines stable
Training: Primary and secondary channels enabled; 100% toggle on all channel lanes;
DRAMs idle; 0% bandwidth; CKE HIGH; Command and address lines stable; DDR2 SDRAM
clock active
IBIST over all IBIST modes: DRAM idle (0% bandwidth); Primary channel enabled; Secon-
dary channel enabled; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active
Electrical idle: DRAM idle (0% bandwidth); Primary channel disabled; Secondary channel
disabled; CKE LOW; Command and address lines floated; DDR2 SDRAM clock active; ODT and
CKE driven LOW
1. Actual test conditions may vary from published JEDEC test conditions.
I
I
I
I
DD_IDLE_1
DD_IDLE_1
DD_IDLE_1
DD_IDLE_1
3000
1060
3000
1060
3400
1105
TBD
TBD
TBD
6.7
6.7
7.5
512MB, 1GB (x72, SR) 240-Pin DDR2 SDRAM FBDIMM
I
I
I
I
DD_ACTIVE_1
DD_ACTIVE_1
DD_ACTIVE_1
DD_ACTIVE_1
3400
2185
3400
2065
3900
2372
14.6
TBD
TBD
TBD
9.5
9.3
9
I
I
I
I
DD_ACTIVE_2
DD_ACTIVE_2
DD_ACTIVE_2
DD_ACTIVE_2
3700
1105
3200
1060
3200
1060
TBD
TBD
TBD
7.9
7.1
7.1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
I
DD
I
I
I
I
DD_TRAINING
DD_TRAINING
DD_TRAINING
DD_TRAINING
Conditions and Specifications
4000
1105
3500
1060
3500
1060
TBD
TBD
TBD
8.4
7.5
7.5
I
I
I
I
DD_IBIST
DD_IBIST
© 2005 Micron Technology, Inc. All rights reserved.
DD_IBIST
DD_IBIST
3800
1060
3800
1060
4500
1105
TBD
TBD
TBD
8.0
8.0
9.2
I
I
2000
2000
I
I
DD_EI
DD_EI
2500
263
263
DD_EI
DD_EI
TBD
TBD
TBD
3.6
3.6
263
4.4
Units
Units
Units
Units
mA
mA
mA
mA
mA
mA
mA
mA
W
W
W
W