STM32W108HBU6 STMicroelectronics, STM32W108HBU6 Datasheet - Page 98
STM32W108HBU6
Manufacturer Part Number
STM32W108HBU6
Description
Manufacturer
STMicroelectronics
Datasheet
1.STM32W108HBU6.pdf
(208 pages)
Specifications of STM32W108HBU6
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Processing Unit
Microprocessor
Operating Supply Voltage (min)
1.18V
Operating Supply Voltage (typ)
1.25V
Operating Supply Voltage (max)
1.32V
Package Type
VFQFPN EP
Pin Count
40
Mounting
Surface Mount
Rad Hardened
No
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Manufacturer
Quantity
Price
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Serial interfaces
9.13.2
98/208
31
15
Reserved
Bits [12:10] SC_RXSSEL: Status of the receive count saved in SCx_RXCNTSAVED (SPI slave mode)
30
14
Serial DMA status register (SCx_DMASTAT)
Address offset: 0xC82C (SC1_DMASTAT) and 0xC02C (SC2_DMASTAT)
Reset value:
Bit 1 SC_RXLODB: Setting this bit loads DMA receive buffer B addresses and allows the DMA
Bit 0 SC_RXLODA: Setting this bit loads DMA receive buffer A addresses and allows the DMA
Bit 9 SC_RXFRMB: This bit is set when DMA receive buffer B reads a byte with a frame error from
Bit 8 SC_RXFRMA: This bit is set when DMA receive buffer A reads a byte with a frame error from
Bit 7 This bit is set when DMA receive buffer B reads a byte with a parity error from the receive FIFO.
29
13
controller to start processing receive buffer B. If both buffer A and B are loaded simultaneously,
buffer A will be used first. This bit is cleared when DMA completes. Writing a zero to this bit has
no effect.
Reading this bit returns DMA buffer status:
0: DMA processing is complete or idle.
1: DMA processing is active or pending.
controller to start processing receive buffer A. If both buffer A and B are loaded simultaneously,
buffer A will be used first. This bit is cleared when DMA completes. Writing a zero to this bit has
no effect.
Reading this bit returns DMA buffer status:
0: DMA processing is complete or idle.
1: DMA processing is active or pending.
when nSSEL deasserts. Cleared when a receive buffer is loaded and when the receive DMA is
reset.
the receive FIFO. It is cleared the next time buffer B is loaded or when the receive DMA is reset.
(SC1 in UART mode only)
the receive FIFO. It is cleared the next time buffer A is loaded or when the receive DMA is reset.
(SC1 in UART mode only)
It is cleared the next time buffer B is loaded or when the receive DMA is reset. (SC1 in UART
mode only)
0: No count was saved because nSSEL did not deassert.
2: Buffer A's count was saved, nSSEL deasserted once.
3: Buffer B's count was saved, nSSEL deasserted once.
6: Buffer A's count was saved, nSSEL deasserted more than once.
7: Buffer B's count was saved, nSSEL deasserted more than once.
1, 4, 5: Reserved.
28
12
SC_RXSSEL
27
11
r
0x0000 0000
26
10
SC_RX
FRMB
25
9
r
Doc ID 16252 Rev 7
SC_RX
FRMA
24
8
r
Reserved
SC_RX
PARB
23
7
r
SC_RX
PARA
22
6
r
SC_RX
OVFB
21
5
r
STM32W108CB, STM32W108HB
SC_R
XOVF
20
A
4
r
SC_TX
ACTB
19
3
r
SC_TX
ACTA
18
2
r
SC_RX
ACTB
17
1
r
SC_RX
ACTA
16
0
r