MT48H4M16LFB4-75 Micron Technology Inc, MT48H4M16LFB4-75 Datasheet
MT48H4M16LFB4-75
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MT48H4M16LFB4-75 Summary of contents
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... Industrial (-40°C to +85°C) • Die revision designator PDF: 09005aef8237ed98, Source: 09005aef8237ed68 64mb_x16_Mobile SDRAM_Y24L_1.fm - Rev. B 10/06 EN Products and specifications discussed herein are subject to change by Micron without notice. 64Mb: 4 Meg x 16 Mobile SDRAM www.micron.com/support Figure 1: 54-Ball VFBGA Ball Assignment (Top View) ...
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... Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Timing Diagrams .47 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 PDF: 09005aef8237ed98, Source: 09005aef8237ed68 64Mb_x16_Mobile SDRAM_Y24LTOC.fm - Rev. B 10/06 EN 64Mb: 4 Meg x 16 Mobile SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 2 ©2006 Micron Technology, Inc. All rights reserved. Table of Contents ...
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... WRITE – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Figure 49: 54-Ball VFBGA (8mm x 8mm .64 PDF: 09005aef8237ed98, Source: 09005aef8237ed68 64Mb_x16_Mobile SDRAM_Y24LLOF.fm - Rev. B 10/06 EN 64Mb: 4 Meg x 16 Mobile SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 3 ©2006 Micron Technology, Inc. All rights reserved. List of Figures ...
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... Table 23 Self Refresh Current Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 DD Table 24: Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 PDF: 09005aef8237ed98, Source: 09005aef8237ed68 64Mb_x16_Mobile SDRAM_Y24LLOT.fm - Rev. B 10/06 EN 64Mb: 4 Meg x 16 Mobile SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 4 ©2006 Micron Technology, Inc. All rights reserved. List of Tables ...
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... A0–A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable read or write burst lengths loca- tions with a burst terminate option. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence ...
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... The 64Mb SDRAM is designed to operate in 1.8V, low-power memory systems. An auto refresh mode is provided, along with a power-saving, deep power-down mode. All inputs and outputs are LVTTL-compatible. SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address ...
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... PDF: 09005aef8237ed98, Source: 09005aef8237ed68 64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. B 10/06 EN Type Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. ...
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... Functional Description The 64Mb SDRAMs (1 Meg banks) are quad-bank DRAMs that operate at 1.8V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16’s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. ...
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... Burst Length Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 4 on page 11. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command ...
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... Meg x 16 Mobile SDRAM Type = Interleaved 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. ...
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... M10 = “0, 0” to ensure compatibility with future devices M6- Defined - - Write Burst Mode M9 0 Programmed Burst Length 1 Single Location Access Micron Technology, Inc., reserves the right to change products or specifications without notice. 11 64Mb: 4 Meg x 16 Mobile SDRAM Address Bus Mode Register (Mx) Burst Length Burst Length ...
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... Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. PDF: 09005aef8237ed98, Source: 09005aef8237ed68 64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. B 10/06 EN 64Mb: 4 Meg x 16 Mobile SDRAM READ NOP ...
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... Temperature Compensated Self Refresh (TCSR) Every cell in the SDRAM requires refreshing due to the capacitor losing its charge over time. The refresh rate is dependent on temperature. At higher temperatures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed more often ...
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... One Bank (Bank RFU RFU 0 1 1/2 Bank (Bank 1/4 Bank (Bank RFU 14 64Mb: 4 Meg x 16 Mobile SDRAM Address Bus 0 Extended Mode Register (Ex Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. ...
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... However, the DQs column reads a “Don’t Care” state to illustrate that the BURST TERMINATE command can occur when there is no data present. PDF: 09005aef8237ed98, Source: 09005aef8237ed68 64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. B 10/06 EN 64Mb: 4 Meg x 16 Mobile SDRAM CS# RAS# CAS# WE# DQM H ...
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... SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese- lected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. ...
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... SELF REFRESH The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down, as long as power is not completely removed from the SDRAM. When in the self refresh mode, the SDRAM retains data without external clocking ...
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... The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of two clocks) for required for the completion of any internal refresh in progress ...
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... Operations Bank/Row Activation Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Figure 7). After opening a row (issuing an ACTIVE command), a READ or WRITE command may be ...
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... READ burst, provided that I/O contention can be avoided given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQ go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. ...
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... NOP NOP NOP READ NOP cycles BANK, BANK, COL n COL OUT OUT CAS Latency = 3 TRANSITIONING DATA Micron Technology, Inc., reserves the right to change products or specifications without notice. 21 64Mb: 4 Meg x 16 Mobile SDRAM T6 NOP D D OUT OUT NOP NOP OUT OUT OUT ...
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... CAS Latency = READ READ READ READ BANK, BANK, BANK, BANK, COL n COL a COL x COL m D OUT DQ n CAS Latency = 3 TRANSITIONING DATA RP is met. 22 64Mb: 4 Meg x 16 Mobile SDRAM T4 T5 NOP NOP D D OUT OUT NOP NOP NOP OUT OUT OUT DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. © ...
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... OUT DON’T CARE READ NOP NOP NOP BANK, COL OUT 23 64Mb: 4 Meg x 16 Mobile SDRAM T4 WRITE BANK, COL NOP WRITE BANK, COL DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. ...
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... TERMINATE BANK, COL OUT OUT CAS Latency = BURST READ NOP NOP NOP TERMINATE BANK, COL n D OUT n CAS Latency = 3 TRANSITIONING DATA 24 64Mb: 4 Meg x 16 Mobile SDRAM NOP NOP ACTIVE cycle BANK a, ROW D D OUT OUT NOP NOP ACTIVE cycles BANK a, ROW D D ...
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... A0-A8 ADDRESS A9, A11 ENABLE AUTO PRECHARGE A10 DISABLE AUTO PRECHARGE BANK BA0, 1 ADDRESS DON’T CARE VALID ADDRESS 25 64Mb: 4 Meg x 16 Mobile SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. ...
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... The 64Mb SDRAM uses a pipe- lined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Figure 19, or each subsequent WRITE may be performed to a different bank ...
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... T2 T3 WRITE NOP READ NOP BANK, BANK, COL n COL 64Mb: 4 Meg x 16 Mobile SDRAM T4 T5 NOP NOP D D OUT OUT DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. ...
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... COL CKS). See Figure 22 on page 29. Micron Technology, Inc., reserves the right to change products or specifications without notice. 28 64Mb: 4 Meg x 16 Mobile SDRAM T6 NOP ACTIVE BANK a, ROW DON’T CARE t RP) after the PRECHARGE command is ©2006 Micron Technology, Inc. All rights reserved. ...
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... CS# WE# All Banks A10 Bank Selected BANK ADDRESS VALID ADDRESS DON’T CARE 29 64Mb: 4 Meg x 16 Mobile SDRAM NOP ACTIVE t RCD t RAS t RC Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. ...
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... READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (M9 = 0). PDF: 09005aef8237ed98, Source: 09005aef8237ed68 64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. B 10/06 EN 64Mb: 4 Meg x 16 Mobile SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 30 ©2006 Micron Technology, Inc. All rights reserved. ...
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... READ NOP NOP NOP BANK, COL OUT OUT 64Mb: 4 Meg x 16 Mobile SDRAM T5 NOP DON’T CARE T5 T6 NOP NOP D D OUT OUT DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. ...
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... Concurrent Auto Precharge Micron SDRAM devices support concurrent auto precharge, which allows an access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing. Four cases where concurrent auto precharge occurs are defined below. READ with Auto Precharge 1. Interrupted by a READ (with or without auto precharge): A READ to bank m will inter- rupt a READ on bank n, two or three clocks later, depending on CAS latency ...
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... WR begins when the READ to bank m is registered. The last valid WRITE t WR begins when the WRITE to bank m is registered. The last valid Micron Technology, Inc., reserves the right to change products or specifications without notice. 33 64Mb: 4 Meg x 16 Mobile SDRAM WRITE - AP NOP ...
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... Page Active WRITE with Burst of 4 Page Active BANK m BANK n, ADDRESS COL Micron Technology, Inc., reserves the right to change products or specifications without notice. 34 64Mb: 4 Meg x 16 Mobile SDRAM NOP NOP NOP NOP Interrupt Burst, Write-Back Precharge BANK BANK BANK m READ with Burst of 4 ...
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... H Notes: 1. CKE clock edge. 2. Current state is the state of the SDRAM immediately prior to clock edge n. 3. COMMAND MAND 4. All states and sequences not shown are illegal or reserved. 5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge (provided that 6 ...
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... Starts with registration of a WRITE command with auto precharge enabled and ends when be in the idle state. 36 64Mb: 4 Meg x 16 Mobile SDRAM is HIGH (see Table 6 on page 35) and has been met. t RCD has been met. No data bursts/ ...
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... May or may not be bank-specific; if all banks are to be precharged, all must valid state for precharging. 8. Deep power-down is power savings feature of this Mobile SDRAM device. This command is BURST TERMINATE when CKE is HIGH and deep power-down when CKE is LOW. 9. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled ...
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... Starts with registration of a WRITE command with auto precharge enabled, and ends when be in the idle state. 38 64Mb: 4 Meg x 16 Mobile SDRAM is HIGH (see Table 6 on page 35) and has been met. t RCD has been met. No data ...
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... WR begins when the READ to bank m is registered. The last valid met, where Micron Technology, Inc., reserves the right to change products or specifications without notice. 39 64Mb: 4 Meg x 16 Mobile SDRAM t WR begins when the WRITE to bank m is reg- ©2006 Micron Technology, Inc. All rights reserved. ...
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... Input low voltage: Logic 0; All inputs PDF: 09005aef8237ed98, Source: 09005aef8237ed68 64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. B 10/06 EN Symbol 1.7V - 1.95V DD DD Symbol -100µA = 100µA ≤ OUT DD Symbol 40 64Mb: 4 Meg x 16 Mobile SDRAM Min Max V 0.35 2 0.35 2.8 DD – 0.35 2.8 – -40 85 Min Max Units 1 ...
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... Refresh period (4,096 rows) AUTO REFRESH period PRECHARGE command period ACTIVE bank a to ACTIVE bank b command Transition time WRITE recovery time Exit SELF REFRESH to ACTIVE command PDF: 09005aef8237ed98, Source: 09005aef8237ed68 64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. B 10/06 EN 64Mb: 4 Meg x 16 Mobile SDRAM -75 Symbol Min Max (3) 6 ...
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... Last data-in to burst STOP command Last data-in to new READ/WRITE command Last data-in to PRECHARGE command LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out to high-impedance from PRECHARGE command PDF: 09005aef8237ed98, Source: 09005aef8237ed68 64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. B 10/06 EN 64Mb: 4 Meg x 16 Mobile SDRAM Symbol -75 t CCD 1 t CKED ...
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... Symbol (MIN RFC = RFC (MIN RFC = 15.625µ Micron Technology, Inc., reserves the right to change products or specifications without notice. 43 64Mb: 4 Meg x 16 Mobile SDRAM Max -75 -8 Units 150 150 µ µA ©2006 Micron Technology, Inc. All rights reserved. Notes 3, 18 12, 19 ...
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... Array 90 1/4 Array, 1/8 Array, and 1/16 Array -50 -40 -30 -20 - Symbol 64Mb: 4 Meg x 16 Mobile SDRAM -75/-8 180 120 130 80 100 80 100 80 100 Temperature (C) Min Max 1.5 4.0 1.5 4.0 3.0 6.0 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... 7.5ns for -75 and CK = 8.0ns for - for a pulse width ≤ 3ns, and the pulse width overshoot: V (MAX 64Mb: 4 Meg x 16 Mobile SDRAM Q = 1.7V - 1.95V 25°C; pin under test biased A ≤ +70°C for commercial parts and REF refresh require- and monotonic manner ...
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... CK = 10ns. 6 limit is actually a nominal value and does not result in a fail value 45°C is sampled only 64Mb: 4 Meg x 16 Mobile SDRAM t RP) begins at 7ns for -8 t RFC (MIN) else CKE is LOW. The Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... RP MRD MRD Load Extended Load Mode Mode Register Register 47 64Mb: 4 Meg x 16 Mobile SDRAM T7 T9 T19 ( ( ( ( ) ) ) ) ( ( ( ( ) ) ) ) ( ( ( ( ) ) ) ) ( ( ( ( ) ...
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... Input buffers gated off while in power-down mode Exit power-down mode Micron Technology, Inc., reserves the right to change products or specifications without notice. 48 64Mb: 4 Meg x 16 Mobile SDRAM CKS NOP ACTIVE ROW ROW BANK All banks idle DON’T CARE ...
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... NOP NOP NOP OUT OUT t LZ Micron Technology, Inc., reserves the right to change products or specifications without notice. 49 64Mb: 4 Meg x 16 Mobile SDRAM NOP WRITE NOP COLUMN e 2 BANK OUT OUT DON’T CARE UNDEFINED ©2006 Micron Technology, Inc. All rights reserved. ...
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... RP t RFC 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. 50 64Mb: 4 Meg x 16 Mobile SDRAM AUTO NOP NOP ACTIVE REFRESH ( ( ) ) ( ( ) ) ( ( ) ...
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... XSR Enter self refresh mode Exit self refresh mode (Restart refresh time base) CLK stable prior to exiting self refresh mode 51 64Mb: 4 Meg x 16 Mobile SDRAM AUTO 1 REFRESH DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... READ NOP NOP NOP t CMH 2 BANK OUT OUT t LZ CAS Latency Micron Technology, Inc., reserves the right to change products or specifications without notice. 52 64Mb: 4 Meg x 16 Mobile SDRAM NOP ACTIVE PRECHARGE ROW ALL BANKS ROW SINGLE BANKS BANK(S) BANK OUT OUT DON’ ...
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... PDF: 09005aef8237ed98, Source: 09005aef8237ed68 64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. B 10/ READ NOP NOP t CMS t CMH COLUMN m 2 BANK OUT t LZ CAS Latency Micron Technology, Inc., reserves the right to change products or specifications without notice. 53 64Mb: 4 Meg x 16 Mobile SDRAM NOP NOP NOP ACTIVE ROW ROW BANK OUT ...
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... CMH 2 COLUMN m ALL BANKS SINGLE BANKS BANK BANK( OUT CAS Latency 54 64Mb: 4 Meg x 16 Mobile SDRAM ACTIVE NOP NOP ROW ROW BANK t RP DON’T CARE UNDEFINED t RAS would be violated Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... CH NOP 3 NOP 3 READ NOP t CMS t CMH COLUMN m 2 ENABLE AUTO PRECHARGE BANK CAS Latency t RAS would be violated. Micron Technology, Inc., reserves the right to change products or specifications without notice. 55 64Mb: 4 Meg x 16 Mobile SDRAM NOP ACTIVE NOP ROW ROW BANK OUT ...
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... SDRAM_Y24L_2.fm - Rev. B 10/ READ NOP ACTIVE t CMS t CMH COLUMN m 2 ROW ROW BANK 0 BANK OUT t LZ CAS Latency - BANK 0 t RCD - BANK 3 56 64Mb: 4 Meg x 16 Mobile SDRAM NOP READ NOP ACTIVE COLUMN b 2 ROW ENABLE AUTO PRECHARGE ROW BANK 3 BANK ...
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... SDRAM_Y24L_2.fm - Rev. B 10/ READ NOP NOP t CMS t CMH COLUMN m 2 BANK OUT CAS Latency 57 64Mb: 4 Meg x 16 Mobile SDRAM NOP NOP NOP OUT OUT Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. T8 NOP DON’ ...
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... 3> and the PRECHARGE command, regardless of fre 64Mb: 4 Meg x 16 Mobile SDRAM NOP PRECHARGE NOP ALL BANKS SINGLE BANK BANK Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. T9 ACTIVE ROW ROW BANK DON’ ...
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... SDRAM_Y24L_2.fm - Rev. B 10/ WRITE NOP NOP NOP t CMH BANK 64Mb: 4 Meg x 16 Mobile SDRAM NOP NOP NOP Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. T9 ACTIVE ROW ROW BANK DON’T CARE ...
Page 60
... NOP 4 WRITE t CMH COLUMN m 3 BANK m> and the PRECHARGE command, regardless of frequency 64Mb: 4 Meg x 16 Mobile SDRAM PRECHARGE NOP ACTIVE ALL BANKS ROW SINGLE BANK BANK BANK RAS would be violated. Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... BANK m> and the PRECHARGE command, regardless of frequency RAS would be violated. 61 64Mb: 4 Meg x 16 Mobile SDRAM ACTIVE NOP NOP ROW ROW BANK t RP Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. ...
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... CH WRITE NOP ACTIVE NOP t CMH ROW ROW BANK RCD - BANK 1 62 64Mb: 4 Meg x 16 Mobile SDRAM WRITE NOP NOP COLUMN b 2 ENABLE AUTO PRECHARGE BANK BANK BANK 0 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. ...
Page 63
... CMS t CMH COLUMN m 2 ENABLE AUTO PRECHARGE DISABLE AUTO PRECHARGE BANK Micron Technology, Inc., reserves the right to change products or specifications without notice. 63 64Mb: 4 Meg x 16 Mobile SDRAM T5 T6 NOP NOP ©2006 Micron Technology, Inc. All rights reserved. T7 NOP DON’T CARE ...
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... Micron Technology, Inc., reserves the right to change products or specifications without notice. 64 64Mb: 4 Meg x 16 Mobile SDRAM Mode Register Definition SOLDER BALL MATERIAL: 96.5% Sn, 3% Ag, 0.5% CU SOLDER MASK DEFINED BALL PADS: Ø0.40 SUBSTRATE MATERIAL: PLASTIC LAMINATE ...