PEB2445NV1.2 Lantiq, PEB2445NV1.2 Datasheet - Page 32

• Manufacturer Part Number: PEB2445NV1.2
• Manufacturer: Lantiq

Specifications of PEB2445NV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

significant bits of the connection memory address and data contain the logical pin
numbers, the most significant bits the time-slot number of the output and input channels.
The following example explains the programming sequence.
Time-slot 7 of the incoming 8192-kbit/s input line IN 14 shall be connected to time-slot 6
of the output line OUT 5 of an 2048-kbit/s system. The attenuation for this connection
should be 7 dB. According to table 8 in 8192-kbit/s systems the input line IN 14 is the
logical input line 2. Output line number and logical output number are identical to one
another. According to chapter 4.5 C3
Therefore the following byte sequence on the address data bus has to be used to
program the CM properly (see table 12):
01101100
00011110
00110101
The frame, for all input channels, starts with the rising edge of the SP signal. The frame
for all output channels begins two
(4096-kHz device clock) before the falling SP edge. The period of time between the
rising and falling edge of the SP pulse should be
Configuration Type
The MUSAC-A works either in the standard configuration for usual switching
applications or in the primary access configuration. In these both configurations the
conference and multipoint switching capability can be used.
Standard Configuration
A logical 1 in the CFS bit of the configuration register sets the PEB 2445 in standard
mode (default after power up). All modes from table 7 can be used. It has to be ensured
that the data rate is not higher than the selected device clock (4096 or 8192 kHz).
In this application 512 channels per frame are written into the speech memory. Each one
of them can be connected to any output channel.
Any output channel can be attenuated independently of each other.
According to table 8 and table 12 and depending on the selected mode the least
t
Semiconductor Group
SPH
= (2 + N
= (1 + N
(Control Byte)
(Data Byte)
(Address Byte)
4)
2)
t
t
CP8
CP4
(0
N
255)
t
or
CP8
(with 8192-kHz device clock) or one
C0 is set to 7
32
01011100
00011110
00110101
H
.
(Control Byte)
(Data Byte)
(Address Byte)
Functional Description
PEB 2445
t
CP4
period
02.96