PEB2445NV1.2 Lantiq, PEB2445NV1.2 Datasheet - Page 39

• Manufacturer Part Number: PEB2445NV1.2
• Manufacturer: Lantiq

Specifications of PEB2445NV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

After resetting the CM, all bits in the CM are reset to 0, except for the D9-bit, which is set
to one, causing the output lines to be tristated.
To prepare the MUSAC-A for programming the CM and CCM, the Rl bit in the mode
register must be reset. Note that one mode register access can serve to reset both RC-
and Rl bits as well as configuring the chip (i.e. selecting operating mode etc.).
Figure 18
Initializing the PEB 2445 for a 8192-kHz Device Clock
3
3.1
After a hardware reset (RES) or power up the MUSAC-A is set to its initial state. The
MOD- and CFR register bits are all set to logical 1; the CSR-, CST- and CMR-register
bits are set to logical 0. The STA register B bit is undefined, the Z bit contains logical 0.
3.2
After reset a few internal signals and clocks need to be initialized. This is done with the
initialization sequence. To give all signals and clocks a defined value only 4 SP pulses
are necessary. The SP pulses may be of any length allowed in normal application, the
time interval between the two SP pulses may be of any length down to 250 ns.
With all signals being defined, the CM needs to be reset. To do that a logical 0 is written
into MOD:RC. STA:B is set. The resulting CM reset is finished after max. 250 s and is
indicated by the status register B bit being logical 0. Changing the pulse shaping factor
N during CM reset may result in a CM-reset time longer than 250 s.
Semiconductor Group
Operational Description
Reset State
Initialization Procedure
39
Operational Description
PEB 2445
02.96