PEB2445NV1.2 Lantiq, PEB2445NV1.2 Datasheet - Page 33

• Manufacturer Part Number: PEB2445NV1.2
• Manufacturer: Lantiq

Specifications of PEB2445NV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

steps. For an example using N = 2 refer to figure 14.
access applications. In this case the MUSAC-A is an interface device connecting a
standard PCM interface (system interface) with another PCM interface e.g. an
intermediate interface for connections to primary loops (synchronous interface). For both
a serial interface is provided.
The synchronous 2048-kbit/s interface consists of four input and four output lines with a
bit rate of 2048-kbit/s. This interface can be used to connect the PEB 2445 to up to four
primary trunk lines via coding/decoding devices with frame alignment function
(e.g. PEB 2035 ACFA) and line transceivers with clock and data recovery
(e.g. PEB 2235 IPAT) and to signaling processors (e.g. the SAB 82520 HSCC).
The system interface is not confined to one data rate but can operate at the full choice
of the PEB 2445 data rates: 2048, 4096 and 8192 kbit/s. A clock shift in a range of
7 1/2 clock steps with half clock step resolution may be programmed independently for
inputs and outputs.
The frame for all input- and output lines starts with the rising edge of the SP signal.
In the primary access mode the signals TSC0, TSC1, TSC2 and TSC3 indicate when the
associated system interface output is valid. The signal DCL supplies a 2-MHz clock
which can be used for other devices at the synchronous interface, e.g. the High Level
Serial Communication Controller HSCC (SAB 82520).
N is an user defined integer. By varying N,
Figure 14
SP Duration for N = 2
Primary Access Configuration
A logical 0 in the CFS bit of the configuration register selects the PEB 2445 for primary
Semiconductor Group
33
t
SPH
can be varied in 2048-kHz clock period
Functional Description
PEB 2445
02.96