MCC501RX200TD0B Freescale Semiconductor, MCC501RX200TD0B Datasheet
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... Data Sheet C-5 NETWORK PROCESSOR SILICON REVISION D0 C5NPD0-DS/D Rev 04 ...
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... Data Sheet C-5 Network Processor Silicon Revision D0 C5NPD0-DS/D Rev 04 ...
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...
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CONTENTS About This Guide Data Sheet Description and Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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CONTENTS Signals Grouped by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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C 4 Mechanical Specifications HAPTER Package Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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CONTENTS C5NP ...
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... MDIO Serial Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Low Speed Serial Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PROM Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Fabric Processor Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 BMU Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 TLU Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 QMU Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-5 Network Processor BGA Package Side View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 27 C-5 Network Processor BGA Package (Bottom View C5NPD0-DS/D Rev ...
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C5NP ...
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... List of Tables List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Navigating Within a C-Port Electronic Document C-5 Network Processor Data Sheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-Port Silicon Documentation Set TLU SRAM Configurations Clock and Reference Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... JTAG Identification Code and Its Sub-components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Register Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-5 Network Processor Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-5 Network Processor Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . C-5 Network Processor DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... ABOUT THIS GUIDE Data Sheet Description This data sheet describes the C-5 Network processor, Version D0. It provides hardware and Organization layout specifications including pinouts, memory configuration guidelines, timing diagrams, power and power sequencing guidelines, thermal design guidelines, and mechanical specifications. The data sheet is divided into the following topics: • ...
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To move to the beginning or end of the document, to move page by page within the document navigate among the pages you displayed by clicking on hyperlinks, use the Acrobat Reader navigation buttons shown in this ...
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Warning: This icon and text indicate a procedure where the reader must take precautions regarding laser light. This icon and text indicate the possibility of electro-static discharge (ESD procedure that requires the reader to take the proper ESD ...
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... Table 2 C-5 Network Processor Data Sheet Revision History REVISION DATE August 8, 2000 March 26, 2001 C5NP CHANGE Operating temperatiure range added. Power sequencing diagram updated. BMU timing diagram updated. TLU timing diagram updated. QMU timing diagram updated. Chapter 1 contains the following revisions: • ...
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... Table 2 C-5 Network Processor Data Sheet Revision History REVISION DATE October 1, 2001 September 9, 2002 Related Product The following table lists the C-5 and CST documentation set. Find the latest editions of Documentation these documents for your installed CST version in the Support section of the C-Port ...
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... Table 3 C-Port Silicon Documentation Set DOCUMENT SUBJECT DOCUMENT NAME Processor C-5 Network Processor Architecture Guide Information C5NP PURPOSE Describes the full architecture of the C-5 network processor. DOCUMENT ID C5NPARCH-RM/D ...
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Chapter 1 FUNCTIONAL DESCRIPTION Feature List Complete programmability • • Simple programming model • • • • Maximum system flexibility • • • Massive processing power • • Programmability at all levels of the protocol stack: Layers 2-7 Examples of ...
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CHAPTER 1: FUNCTIONAL DESCRIPTION • • • • • • High functional integration • • • • • • Stable programming interfaces • • Third-party support • • C5NP More than 3,000MIPs of computing power (for adding services throughout ...
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... Block Diagram The C-5 applications. interfaces. The following sections describe each component of the C-5 NP. For more information about the architecture of the C-5 NP, see the C-5 Network Processor Architecture Guide. Figure 1 C-5 Network Processor Block Diagram The main components of the C-5 NP are: • ...
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CHAPTER 1: FUNCTIONAL DESCRIPTION Channel Processors The C-5 NP contains sixteen programmable Channel Processors (CPs) that receive, process, and transmit network data. The number of CPs per port is configurable, depending on the line interface. Typically one CP is ...
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System Interfaces The system interfaces to the XP are: • • • Fabric Processor The Fabric Processor (FP) acts as a high-speed network interface port with advanced functionality. It allows the C interface to an application-specific ...
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... CHAPTER 1: FUNCTIONAL DESCRIPTION or cells from the C hardware interface that provides connectivity to other network processors or other similar line processing hardware. There are numerous parameters that can be configured within the FP to allow the interface to be adapted to different fabric protocols. The FP is Utopia-1, 2 and Utopia-3, IBM PRIZMA, and PowerX (Csix-L0) compatible ...
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QoS lookup tasks. The C-5 NP uses external 64bit wide ZBT Pipelined Bursting Static RAM (SRAM) modules (at frequencies to 133MHz) for ...
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CHAPTER 1: FUNCTIONAL DESCRIPTION C5NP ...
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... Chapter 2 SIGNAL DESCRIPTIONS Signal Summary There are ten functional groupings of signals in the C-5 network processor: • • • • • • • • • • Two of the sections (CPs and FP) are configurable, depending on the type of device being implemented. Pinout Diagram The C-5 NP contains 838 pins as shown in throughout the remaining chapter. Clock — ...
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CHAPTER 2: SIGNAL DESCRIPTIONS Figure 2 Pin Locations (Bottom View) Pin Descriptions Grouped The C-5 NP pins are categorized in groups, reflecting interfaces to the chip: by Function • • • C5NP Clock Signals CP Interface Signals Executive Processor ...
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Fabric Processor Interface Signals • BMU SDRAM Interface Signals • TLU SRAM Interface Signals • QMU SRAM Interface Signals • Power Supply Signals • Test Signals • No Connection Pins LVTTL and LVPECL C-5 NP pins are the following ...
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CHAPTER 2: SIGNAL DESCRIPTIONS Table 5 Clock and Reference Signals (continued) SIGNAL NAME CPREF‡ TOTAL * SCLK and SCLKX must not be AC-coupled. † The frequencies specified for CCLK0 - CCLK7 allow full flexibility for the C-5 NP. Clock ...
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Gigabit Ethernet and Fibre Channel TBI Configuration • SONET OC-3 Transceiver Interface Configuration • SONET OC-12 Transceiver Interface Configuration Table 6 CP Physical Interface Signals and Pins (Grouped by Clusters) CP CLUSTER 1 CP CLUSTER 2 SIGNAL PIN # ...
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CHAPTER 2: SIGNAL DESCRIPTIONS Table 6 CP Physical Interface Signals and Pins (Grouped by Clusters) (continued) SIGNAL CP3_2 CP3_3 CP3_4 CP3_5 CP3_6 DS1/T1 Framer Interface Configuration Table 7 implement one serial Framer interface. Table 7 DS1/T1 Framer Interface Signals ...
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Table 8 10/100 Ethernet Signals SIGNAL NAME* PIN # TOTAL TYPE CPn_0 Table 6 1 LVTTL CPn_1 Table 6 1 LVTTL CPn_2 Table 6 1 LVTTL CPn_3 Table 6 1 LVTTL CPn_4 Table 6 1 LVTTL CPn_5 Table 6 1 ...
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CHAPTER 2: SIGNAL DESCRIPTIONS Figure 3 GMII/TBI Transmit and Receive Pin Configurations The unused CP pins in the two cluster configurations should be wired to ground using a resistor. Table 10 Gigabit Ethernet (GMII/MII) Signals One Cluster Example SIGNAL ...
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Table 10 Gigabit Ethernet (GMII/MII) Signals One Cluster Example (continued) SIGNAL NAME* PIN #† TOTAL TYPE CPn+1_4 Table 6 1 LVTTL CPn+1_5 Table 6 1 LVTTL CPn+1_6 Table 6 1 LVTTL CPn+2_0 Table CPn+2_1 Table 6 1 ...
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CHAPTER 2: SIGNAL DESCRIPTIONS use and the signals and pinouts for a single cluster for Gigabit Ethernet and Fibre Channel TBI. The unused pins for the two cluster configurations should be wired down using a resistor. Table 11 Gigabit ...
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Table 11 Gigabit Ethernet and Fibre Channel TBI Signals Example (continued) SIGNAL NAME* PIN #† TOTAL TYPE CPn+3_2 Table 6 1 LVTTL CPn+3_3 Table 6 1 LVTTL CPn+3_4 Table 6 1 LVTTL CPn+3_5 Table 6 1 LVTTL CPn+3_6 Table 6 ...
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CHAPTER 2: SIGNAL DESCRIPTIONS Table 13 OC-12 Signals Example SIGNAL NAME* PIN #† TOTAL TYPE CPn_0 Table 6 1 LVTTL CPn_1 Table 6 1 LVTTL CPn_2 Table 6 1 LVTTL CPn_3 Table 6 1 LVTTL CPn_4 Table 6 1 ...
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Table 13 OC-12 Signals Example (continued) SIGNAL NAME* PIN #† TOTAL TYPE CPn+3_5 Table 6 1 LVTTL CPn+3_6 Table TOTAL PINS * n can † Reference Table 6 for pin ...
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CHAPTER 2: SIGNAL DESCRIPTIONS Table 14 PCI Signals (continued) SIGNAL NAME PIN # PSTOPX K18 PDEVSELX N18 PPERRX M18 PSERRX L18 PCLK L15 PRSTX N17 PREQX L17 PGNTX N19 PIDSEL O18 PINTA O16 TOTAL PINS Serial Interface Signals The ...
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Table 15 Serial Port Signals SIGNAL NAME PIN # TOTAL SICL O14 1 SIDA ...
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... Two accesses are piplined together to execute one 32-bit fetch. The steps are shown in Figure 1 The PROM_ADDR is loaded into the network processor internal shift register. 2 The PROM_ADDR is shifted into the external shift register for 22 SPCLK cycles. 3 SPLD is asserted for one SPCLK cycle, loading the PROM_ADDR into the external 4 SPLD is deasserted for 22 SPCLK cycles ...
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... PROM_RETURN_DATA register and the second PROM_DATA into the external shift register. 8 SPLD is deasserted for 22 SPCLK cycles, shifting the second PROM_DATA into the network processor internal shift register. 9 SPLD is asserted for one SPCLK cycle, loading the second PROM_DATA into the network processor PROM_RETURN_DATA register. ...
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CHAPTER 2: SIGNAL DESCRIPTIONS Table 17 General System Interface Signal SIGNAL NAME PIN # TOTAL XPUHOT J19 1 1 TOTAL PINS Fabric Processor Interface The FP consists of two logical signal interfaces: a receive data interface and a transmit ...
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... FRXCTL4 Input n/a FRXCTL5 Input n/a FRXCTL6 Input RxPrty * cell size must be 4Byte aligned. Table 20 Utopia1*, 2*, 3 PHY Mode, C-5 Network Processor to Fabric Interface Pin Mapping RECEIVE SIGNALS C-5 NETWORK PROCESSOR I/O UTOPIA FRXCTL0 Input TxEnb* TOTAL 7 80 Utopia1, Utopia2, Utopia3 ATM Mode mappings ...
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... When configuring two C-5 network processors back-to-back using the Fabric Port, set up the transmit side of each C-5 network processor in Utopia ATM mode and the receive side of each C-5 network processor in Utopia PHY mode. Table 21 PRIZMA Mode, C-5 Network Processor to Fabric Interface Pin Mapping ...
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... Table 22 Power X Mode, C-5 Network Processor to Fabric Interface Pin Mapping RECEIVE SIGNALS C-5 NETWORK PROCESSOR I/O POWER X FRXCTL0 Input RxCtrl[0] FRXCTL1 Input RxCtrl[1] FRXCTL2 Input RxCtrl[2] FRXCTL3 Input RxPrty[3] FRXCTL4 Input RxPrty[2] FRXCTL5 Input RxPrty[1] FRXCTL6 Input RxPrty[0] BMU SDRAM Interface ...
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CHAPTER 2: SIGNAL DESCRIPTIONS Table 23 BMU SDRAM Interface Signals (continued) SIGNAL NAME PIN # MA0 - MA11 H22, I22, H23, H24, I24, H25, H26, I26, H27, H28, I28, H29 MBA0 - MBA1 G18, H19 MCLK I16 MCASX J21 ...
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Table 23 BMU SDRAM Interface Signals (continued) SIGNAL NAME PIN # MDCLK J17 TOTAL PINS TLU SRAM Interface The TLU SRAM interface supports up to 32MBytes of SRAM at frequencies to 133MHz Signals using LVTTL signaling levels (in single bank-mode ...
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CHAPTER 2: SIGNAL DESCRIPTIONS QMU SRAM Interface The QMU signals are described in Signals core clock frequency. Table 26 QMU SRAM Interface Signals SIGNAL NAME PIN # QCPAR A10 QCLK G12 QCMD0 - QCMD15 B10, C10, D10, E10, F10, ...
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Table 27 Power Supply Signals (continued) SIGNAL NAME PIN # VDD33 A7, A19, C9, C21, E11, E23, F12, G1, G13, G25, H14, I3, I15, I27, J16, K5, K17, K29, M7, M19, O9, O21, Q11, Q23, S1, S13, S25, U3, U15, ...
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CHAPTER 2: SIGNAL DESCRIPTIONS Figure 6 Power and Ground Connections (Bottom View) Test Signals Test signals are described in C5NP Table 28 and their pinouts are shown in Figure 6. ...
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Table 28 Miscellaneous Test Signals For JTAG, Scan, and Internal Test Routines SIGNAL NAME PIN # JTCK T11 JTMS* Z15 JTRSTX† X15 JTDI† AB15 JTDO V15 JHIGHZ T12 JCLKBYP T13 JSE S12 JS00-JS09 L12, N13, N12, P13, P12, Q12, R13, ...
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CHAPTER 2: SIGNAL DESCRIPTIONS Table 30 Signals Listed by Pin Number PIN C5NP FUNCTION PIN ...
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Table 30 Signals Listed by Pin Number (continued) PIN FUNCTION PIN FUNCTION D1 QDATA0 D9 QXCTRL0 D2 QDATA5 D10 QCMD2 D3 QDATA8 D11 QCMD6 D4 QDATA13 D12 QCMD11 D5 QDATA17 D13 QCMD14 D6 QDATA22 D14 MECC5 D7 QDATA26 D15 MECC4 ...
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CHAPTER 2: SIGNAL DESCRIPTIONS Table 30 Signals Listed by Pin Number (continued) PIN C5NP FUNCTION ...
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Table 30 Signals Listed by Pin Number (continued) PIN FUNCTION PIN FUNCTION J1 TD2 J9 TD49 J2 TD10 J10 TD50 J3 TD13 J11 TD62 J4 TD21 J12 VDD J5 TD26 J13 CCLK1 J6 TD33 J14 VSS J7 TD37 J15 CCLK2 ...
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CHAPTER 2: SIGNAL DESCRIPTIONS Table 30 Signals Listed by Pin Number (continued) PIN C5NP FUNCTION ...
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Table 30 Signals Listed by Pin Number (continued) PIN FUNCTION PIN FUNCTION P1 TA1 P9 TD52 P2 TA6 P10 NC5 P3 TA8 P11 NC7 P4 TA13 P12 JSO4 P5 TA16 P13 JSO3 P6 TA20 P14 PPAR P7 TA21X P15 PAD29 ...
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CHAPTER 2: SIGNAL DESCRIPTIONS Table 30 Signals Listed by Pin Number (continued) PIN C5NP FUNCTION ...
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Table 30 Signals Listed by Pin Number (continued) PIN FUNCTION PIN FUNCTION V1 FIN1 V9 FIN23 V2 FIN3 V10 FIN26 V3 FIN5 V11 FIN31 V4 FIN9 V12 FRXCTL2 V5 FIN10 V13 FRXCTL5 V6 FIN14 V14 NC9 V7 FIN18 V15 JTDO ...
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CHAPTER 2: SIGNAL DESCRIPTIONS Table 30 Signals Listed by Pin Number (continued) PIN AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 C5NP FUNCTION ...
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Table 30 Signals Listed by Pin Number (continued) PIN AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 JTAG Support The C-5 NP contains JTAG test logic compliant with the IEEE 1149.1 specification. ...
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CHAPTER 2: SIGNAL DESCRIPTIONS JTAG Data Registers The C-5 NP contains the standard internal registers as specified in IEEE 1149.1. These registers are described in Table 31 JTAG Internal Register Descriptions REGISTER NAME Bypass Boundary Device Identification Boundary Scan ...
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Figure 8 Cell Design That Can Be Used for Both Input and Output Pins IDcode Register The C-5 NP implements a standard 32bit JTAG identification register. value of the code for full identification and its sub-components. Table 32 JTAG Identification ...
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CHAPTER 2: SIGNAL DESCRIPTIONS Table 33 Instruction Register Instructions (continued) (continued) INSTRUCTION MNEMONIC Sample/Preload Highz Clamp Bypass Reserved* Reserved* Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass * There are two reserved instructions intended for C-Port Corporation’s internal use. ...
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... Storage Temperature Absolute Maximum Junction Temperature * Voltages are relative to Ground † Not to exceed V lists the absolute maximum ratings for the C-5 network processor. Stresses Conditions” (Table Table 34 Reduce device reliability Result in premature device failure, even with no immediate sign of failure Supply Voltage (3.3V input)*† ...
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... CHAPTER 3: ELECTRICAL SPECIFICATIONS Recommended Operating The recommended operating conditions describe an environment the C-5 NP network Conditions processor is expected to encounter during normal operation. recommended operating parameters for the C-5 NP. Table 35 C-5 Network Processor Recommended Operating Conditions PARAMETER V DD33 DD33 Peak values to be used by power supply designer. ...
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... Table 36 C-5 Network Processor DC Characteristics (continued) (continued) PARAMETER* LVPECL Output Low Voltage LVPECL Input Current CPREF * All voltages are relative to Ground unless otherwise indicated. Each control input pin has a capacitance associated with it. The capacitance at the control input is due to the package and the input circuitry connected to the pin. Capacitance is based on these conditions: T capacitance data ...
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... CHAPTER 3: ELECTRICAL SPECIFICATIONS Figure 9 Bringup Clock Timing Diagram Power and Thermal Table 38 Characteristics version (Revision D0) of the C-5 NP. Table 38 C-5 Network Processor Power and Thermal Characteristics PARAMETER Power Dissipation, P Maximum Junction Temperature, T Thermal Resistance, junction to case, φ Thermal Resistance, junction to ambient, φ ...
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... Table 38 C-5 Network Processor Power and Thermal Characteristics (continued) PARAMETER MIN TYP Thermal Resistance, Junction 6.0 through Board to Ambient, φ JBA Effective Thermal Resistance, 1.43 φ effective Notes for Table 38: 1 Estimated power dissipation (+/-10%) is derived from measurements on the C-5 NP Revision D00 under following conditions: • ...
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... CHAPTER 3: ELECTRICAL SPECIFICATIONS 3 Effective Thermal Resistance (φ Figure 10 Thermal Performance for C-5 Network Processor Heat Sink (see AC Timing Specifications AC timing specifications consist of input requirements and output responses. The input requirements include setup and hold times, pulse widths, and high and low times. The output responses include delays from clock to signal ...
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See Figure 11. Output timing specifications for LVTTL pins are given with a 10pF load on the output. Other loads can be simulated with the IBIS model available from C-Port. The LVPECL driver is specified into a 50Ω load terminated ...
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CHAPTER 3: ELECTRICAL SPECIFICATIONS Table 39 System Clock Timing Description MIN SYMBOL PARAMETER 1X CLK MODE Tsc System Cycle Time 6.0 5.0 4.3 Tsh Sys Clk High Pulse 45 Tsl Sys Clk Low Pulse 45 Tcc0 CCLK0 Cycle Time ...
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Gigabit TBI Interface Timing Description • OC-12 Timing Description DS1/DS3 Timing Specifications The DS1/DS3 interface timing is shown in Figure 13 DS1/DS3 Ethernet Timing Diagram Table 40 DS1/DS3 Ethernet Timing Description SYMBOL PARAMETER Tcdt DS1/DS3 Transmit Cycle Time Tcdo ...
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CHAPTER 3: ELECTRICAL SPECIFICATIONS Figure 14 10/100 Ethernet Timing Diagram Table 41 10/100 Ethernet Timing Description SYMBOL Tcet Tceo Tces Tceh * STD/Fast Ethernet Gigabit GMII Ethernet, TBI and MII Interface Timing Specifications The Gigabit GMII Ethernet interface timing ...
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Figure 15 Gigabit Ethernet and TBI Interface Timing Diagram GMII / TBI Tx Cycle 1 CPn_0 (TCLK) CPn_2-6 (Tx) CPn+1_2-6 (Tx) MII Tx Cycle 1 MII CPn_1 (TCLK) MII CPn_2-6 (Tx) TBI Rx Cycle 1 CPn+2_1 (RCLKN) CPn+3_1 (RCLK) T ...
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CHAPTER 3: ELECTRICAL SPECIFICATIONS Table 42 Gigabit GMII/MII Ethernet Interface Timing Description SYMBOL GIGABIT Tcgt Tcgo Tcgr Tcgs Tcgh Tcmt Tcmo Table 43 Gigabit TBI Interface Timing Description SYMBOL TBI Tctt Tcto Tctr Tctd Tcts Tcth * For Fibre ...
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Figure 16 OC-3 Timing Diagram Table 44 OC-3 Timing Description SYMBOL PARAMETER Tc3t OC-3 Transmit Cycle Time Tc3i OC-3 Pulse Width Tc3r OC-3 Receive Cycle Time* Tc3d OC-3 Clock Duty Cycle Tc3s OC-3 Setup Time Tc3h OC-3 Hold Time * ...
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CHAPTER 3: ELECTRICAL SPECIFICATIONS OC-12 Timing Specifications The OC-12 interface timing is shown in Figure 17 OC-12 Timing Diagram Table 45 OC-12 Timing Description SYMBOL Tc12i Tc12d Tc12t Tc12o Tc12r Tc12s Tc12h * Input from PHY † Output from ...
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Executive Processor The XP timing specifications include: Timing Specifications • PCI Timing Specifications • MDIO Serial Interface Timing Specifications • Low Speed Serial Interface Timing Specifications • PROM Interface Timing Specifications PCI Timing Specifications The PCI timing is shown in ...
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CHAPTER 3: ELECTRICAL SPECIFICATIONS Table 46 PCI Timing Description (continued) (continued) SYMBOL Tpah Tpao Tpaz Tpav Tpgs Tpgh Tpis Tpih * 66MHz PCI † P_ctl includes all PCI control parameters including: PPAR, PFRAMEX, PTRDYX, PIRDYX, PSTOPX, PDEVSELX, PPERRX, PSERRX ...
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Table 47 MDIO Serial Interface Timing Description SYMBOL PARAMETER MIN Tsic SICL Cycle Time 40 Tsids SIDA Input Setup 10 Tsidh SIDA Input Hold 0.0 Tsods SIDA Output Setup 10 Tsodh SIDA Output Hold 10 Low Speed Serial Interface Timing ...
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CHAPTER 3: ELECTRICAL SPECIFICATIONS Table 48 Low Speed Serial Interface Timing Description (continued) (continued) SYMBOL Tbuf Cmax PROM Interface Timing Specifications The PROM interface timing is shown in Figure 21 PROM Interface Timing Diagram Table 49 PROM Interface Timing ...
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Fabric Processor Timing The FP timing specifications are shown in Specifications Figure 22 Fabric Processor Timing Diagram Table 50 Fabric Processor Timing Description SYMBOL Tfrc Tfrcs Tfrch Figure 22 PARAMETER MIN TYP FRX Cycle Time 9.0 FRXCTL Setup 4.0 1.5 ...
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CHAPTER 3: ELECTRICAL SPECIFICATIONS Table 50 Fabric Processor Timing Description (continued) SYMBOL Tfrco Tfrcz Tfrcv Tfrds Tfrdh Tftc Tftcs Tftch Tftco Tftcz Tftcv Tftdo * Not fully tested, values based on design/characterization. BMU Timing The BMU timing specifications are ...
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Figure 23 BMU Timing Diagram Table 51 BMU Timing Description SYMBOL PARAMETER Tmc BMU Cycle Time Tmco BMU Ctrl Output Tmao BMU Addr Output Tmds BMU Data Setup Tmdh BMU Data Hold Tmdo BMU Data Output Tmdz BMU Data Clk ...
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CHAPTER 3: ELECTRICAL SPECIFICATIONS TLU Timing Specifications The TLU timing specifications are shown in Figure 24 TLU Timing Diagram Table 53 TLU Timing Description SYMBOL Ttc Ttco Ttao Ttds Ttdh Ttdo Ttdz Ttdv * Not fully tested, values based ...
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Table 54 Signal Groups in TLU Timing Diagrams SIGNAL GROUP Data (TDn) QMU Timing The QMU timing specifications are shown in Specifications Figure 25 QMU Timing Diagram Table 55 QMU Timing Description SYMBOL PARAMETER Tqc QMU Cycle Time Tqco QMU ...
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CHAPTER 3: ELECTRICAL SPECIFICATIONS Table 55 QMU Timing Description (continued) (continued) SYMBOL Tqdv * Not fully tested, values based on design/characterization. Table 56 Signal Groups in QMU Timing Diagrams SIGNAL GROUP QCMDn QDATAn C5NP PARAMETER MIN TYP QMU Data ...
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... Chapter 4 MECHANICAL SPECIFICATIONS Package Views The C-5 network processor is an 838 pin (29 pins x 29 pins) Ball Grid Array (BGA) package as shown in the following illustrations. Figure 26 C-5 Network Processor BGA Package Side View HiTCE: Green ceramic is thermally matched to FR4 circuit board. The aluminum lid is electrically connected to the grounded substrate of the C-5 NP. ...
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... CHAPTER 4: MECHANICAL SPECIFICATIONS Figure 27 C-5 Network Processor BGA Package (Bottom View) Package Measurements Table 57 maximum sizes where appropriate. C5NP defines the C-5 NP package measurements, providing nominal, minimum, and ...
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... Marking Codes Table 58 Table 58 C-5 Network Processor Marking Codes MARKING (EXPLANATION OF CODES) Top Bottom Pin 1 Marking Reflow Typical Reflow Profile for the C-5 Switch Module 1 Follow the guidelines recommended by your solder paste supplier. Flux requrements must be met for best solderability. 2 The temperature profile should be carefully characterized to ensure uniform Solder ball voiding may be affected by ramp rates and dwell times below and above liquidus ...
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CHAPTER 4: MECHANICAL SPECIFICATIONS 3 A nitrogen atmosphere is not required, but will make the process more robust. It can 4 Full convection forced air furnaces work best, but IR, Convection/IR, or vapor phase can C5NP make a difference ...
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... C-5 Network Processor BGA Package, Bottom View C-5 Network Processor BGA Package, Side View C-5 Network Processor Capacitance Data 69 C-5 Network Processor DC Characteristics 68 C-5 Network Processor Power and Thermal Characteristics C-5 NP Channel Processors 22 C5NPD0-DS/D Rev 04 Channel Processor Interface Signals Channel Processors ...
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... Signal Groups in BMU Timing 89 Signal Groups in QMU Timing 92 Signal Groups in TLU Timing 90 System Clock Timing 74 TLU Timing 90 Diagram, Block C-5 Network Processor 21 DS1/DS3 Ethernet Timing Description 76 DS1/DS3 Ethernet Timing Diagram 76 DS1/DS3 Timing Specifications 75 DS1/T1 Framer Interface Configuration 32 DS1/T1 Framer Interface Signals ...
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... Pinout Diagram 27 Power and Ground Connections (Bottom View) Power Sequencing 69, 70 Power Supply Signals 50 Power X Mode, Fabric Interface Pin Mapping PRIZMA Mode, C-5 Network Processor to Fabric Interface Pin Mapping 46 Processor, Executive 22 Processor, Fabric PROM Interface Diagram PROM Interface Signals PROM Interface Timing Description ...
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... SONET OC-12 SONET OC-3 Transmit and Receive Pin Combinations for Gigabit Ethernet and FibreChannel U Using C-Port Electronic Documents Utopia2/Utopia3 ATM Mode, C-5 Network Processor to Fabric Interface Pin Mapping Utopia2/Utopia3 PHY Mode, C-5 Network Processor to Fabric Interface Pin Mapping X XP Timing Specifications ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...