MCC501RX200TD0B Freescale Semiconductor, MCC501RX200TD0B Datasheet - Page 39

• Manufacturer Part Number: MCC501RX200TD0B
• Manufacturer: Freescale Semiconductor

Specifications of MCC501RX200TD0B

• Package Type: BGA
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Table 13 OC-12 Signals Example (continued)
*
†
Table 14 PCI Signals
SIGNAL NAME*
CPn+3_5
CPn+3_6
TOTAL PINS
SIGNAL NAME
PAD0 - PAD31
PCBEX0 - PCBEX3
PPAR
PFRAMEX
PTRDYX
PIRDYX
n can be 0, 4, 8, or 12
Reference
System Interface Signals
Executive Processor
Table 6
for pin numbers for a different cluster.
PIN #†
Table 6
Table 6
PIN #
T22, R21, P21, T21, R20, P20, T20,
R19, Q20, S20, R18, P19, T19,
R17, P18, T18, R16, Q18, S18, S16,
P17, T17, R15, P16, T16, S14, Q16,
T15, R14, P15, T14, Q14
N21, N20, M20, O20
P14
K20
L20
L19
TOTAL
1
1
28
The XP’s system interface manages the supervisory controls for the network interfaces, as
well as the set of pins that provide interfaces to other components in the system that are
not memories or network interfaces. It is also the primary interface used for initializing the
C-5 NP after reset. The XP signals include PCI signals, Serial interface signals, and PROM
interface signals.
PCI Signals
The PCI can be configured to support a 32bit PCI capable of operating at either 33MHz or
66MHz. The PCI is fully compliant with PCVI Specification revision 2.1.
the PCI signals.
TYPE
LVTTL
nc
I/O
I
nc
TOTAL
32
4
1
1
1
1
LABEL
RXD(7)
nc
TYPE
PCI
PCI
PCI
PCI
PCI
PCI
SIGNAL DESCRIPTION
Receive Data (most significant bit)
nc
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SIGNAL DESCRIPTION
Multiplexed Address/Data Bus. These signals are
multiplexed address and data bits. The C-5 NP
receives addresses as target and drives addresses as
master. It drives the data and receives read data as
master.
Command byte enables. These signals are
multiplexed command and byte enabled signals.
The C-5 NP receives byte enables as target and drives
byte enables as master.
Parity. This signal carries even parity for AD and CBE#
pins. It has the same receive and drive characteristics
as the address and data bus, except that it is one PCI
cycle later.
Cycle frame
Target ready for data transfer
Initiator ready for data transfer
Pin Descriptions Grouped by Function
Table 14
describes
V 04
39