SC2200UFH233F33 AMD (ADVANCED MICRO DEVICES), SC2200UFH233F33 Datasheet - Page 135

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SC2200UFH233F33

Manufacturer Part Number
SC2200UFH233F33
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet

Specifications of SC2200UFH233F33

Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / Rohs Status
Compliant
SuperI/O Module
5.8.3
This section describes the IRCP/SP3 support registers.
The IRCP/SP3 functional block provides advanced, versa-
tile serial communications features with IR capabilities.
The IRCP/SP3 also supports two DMA channels; the func-
tional block can use either one or both of them. One chan-
nel is required for IR-based applications, since IR
communication works in half duplex fashion. Two channels
would normally be needed to handle high-speed full duplex
IR based applications.
The IRCP or Serial Port 3 is chosen via bit 6 of the PMR
Register (see Section 4.2 "Multiplexing, Interrupt Selection,
and Base Address Registers" on page 76).
5.8.3.1
Eight register banks, each containing eight registers, con-
trol IR/SP3 operation. All registers use the same 8-byte
address space to indicate offsets 00h through 07h. The
BSR register selects the active bank and is common to all
banks. See Figure 5-19.
5.8.3.2
The tables in this subsection provide register and bit maps
for Banks 0 through 7.
1.
AMD Geode™ SC2200 Processor Data Book
When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 5-47.
Offset
00h
01h
02h
03h
04h
05h
06h
07h
IR Communications Port (IRCP) / Serial
Port 3 (SP3) Functionality
IR/SP3 Mode Register Bank Overview
IRCP/SP3 Register and Bit Maps
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
W
W
Name
RXD. Receive Data Port
TXD. Transmit Data Port
IER. Interrupt Enable
EIR. Event Identification
FCR. FIFO Control
LCR
BSR
MCR. Modem/Mode Control
LSR. Link Status
MSR. Modem Status
SPR. Scratchpad
ASCR. Auxiliary Status and Control
Table 5-46. Bank 0 Register Map
1
1
. Link Control
. Bank Select
Figure 5-19. IRCP/SP3 Register Bank
Offset 07h
Offset 06h
Offset 05h
Offset 04h
Offset 02h
Offset 01h
Offset 00h
LCR/BSR
Bank 0
Bank 1
Bank 2
Architecture
Bank 3
Bank 4
32580B
Bank 5
Bank 6
Common
Register
Throughout
All Banks
Bank 7
141

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