SC2200UFH233F33 AMD (ADVANCED MICRO DEVICES), SC2200UFH233F33 Datasheet - Page 59

• Manufacturer Part Number: SC2200UFH233F33
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC2200UFH233F33

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Compliant

Signal Definitions
3.4.9
AMD Geode™ SC2200 Processor Data Book
Signal Name
IDE_RST#
IDE_ADDR2
IDE_ADDR1
IDE_ADDR0
IDE_DATA[15:0]
IDE_IOR0#
IDE_IOR1#
IDE_IOW0#
IDE_IOW1#
IDE_CS0#
IDE_CS1#
IDE_IORDY0
IDE_IORDY1
IDE_DREQ0
IDE_DREQ1
IDE_DACK0#
IDE_DACK1#
IRQ14
IRQ15
IDE Interface Signals
Table 3-3
Ball No.
on page
AD3
AD2
AD1
AC4
AD4
AA1
AE1
See
D28
C28
AF2
B29
C31
C30
AF1
AJ8
41.
U2
Y4
P2
Type
I/O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
Description
IDE Reset. This signal resets all the devices that are
attached to the IDE interface.
IDE Address Bits. These address bits are used to
access a register or data port in a device on the IDE bus.
IDE Data Lines. IDE_DATA[15:0] transfers data to/from
the IDE devices.
IDE I/O Read Channels 0 and 1. IDE_IOR0# is the read
signal for Channel 0 and IDE_IOR1# is the read signal
for Channel 1. Each signal is asserted at read accesses
to the corresponding IDE port addresses.
IDE I/O Write Channels 0 and 1. IDE_IOW0# is the
write signal for Channel 0. IDE_IOW1# is the write signal
for Channel 1. Each signal is asserted at write accesses
to corresponding IDE port addresses.
IDE Chip Selects 0 and 1. These signals are used to
select the command block registers in an IDE device.
I/O Ready Channels 0 and 1. When de-asserted, these
signals extend the transfer cycle of any host register
access if the required device is not ready to respond to
the data transfer request.
Note:
DMA Request Channels 0 and 1. The IDE_DREQ sig-
nals are used to request a DMA transfer from the
SC2200. The direction of transfer is determined by the
IDE_IOR/IOW signals.
Note:
DMA Acknowledge Channels 0 and 1. The
IDE_DACK# signals acknowledge the DREQ request to
initiate DMA transfers.
Interrupt Request Channels 0 and 1. These input sig-
nals are edge-sensitive interrupts that indicate when the
IDE device is requesting a CPU interrupt service.
Note:
If selected as IDE_IORDY0 or IDE_IORDY1
function(s) but not used, then signal(s) should be
tied high.
If selected as IDE_DREQ0/ IDE_DREQ1 func-
tion but not used, tie IDE_DREQ0/IDE_DREQ1
low.
If selected as IRQ14/IRQ15 function but not
used, tie IRQ14/IRQ15 low.
32580B
muxed with the TFT
interface. See Table
The IDE interface is
BOUT2+SDTEST5
3-5 on page 46 for
GPIO10+DSR2#+
GPIO9+DCD2#+
GPIO6+DTR2#/
GPIO8+CTS2#
GPIO7+RTS2#
GPIO11+RI2#
+SDTEST4
+SDTEST0
SDTEST2
SDTEST1
TFTDCK
TFTD10
TFTD11
TFTD4
TFTD2
TFTD3
details.
TFTD9
TFTD5
TFTDE
TFTD8
TFTD0
TFTD1
Mux
63