PNX1701EH,557 NXP Semiconductors, PNX1701EH,557 Datasheet - Page 485
PNX1701EH,557
Manufacturer Part Number
PNX1701EH,557
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1701EH557.pdf
(832 pages)
Specifications of PNX1701EH,557
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / Rohs Status
Not Compliant
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Philips Semiconductors
Volume 1 of 1
Table 3: Fast general purpose output (FGPO)
PNX17XX_SER_1
Preliminary data sheet
Bit
1:0
Offset 0x07,1018
31:24
23:0
Offset 0x07,101C
31:24
23:0
Offset 0x07,1020
31:24
23:0
Offset 0x07,1024
31:24
23:0
Offset 0x07,1028
31:24
23:0
Offset 0x07,102C
31:24
23:0
Offset 0x07,1030
31:0
Offset 0x07,1034
31:0
Symbol
Reserved
Reserved
NREC1
Reserved
NREC2
Reserved
THRESH1
Reserved
THRESH2
Reserved
REC_GAP
Reserved
BUF_GAP
TIME1
TIME2
4.2 Status Registers
FGPO_NREC1
FGPO_NREC2
FGPO_THRESH1
FGPO_THRESH2
FGPO_REC_GAP
FGPO_BUF_GAP
FGPO_TIME1
FGPO_TIME2
Acces
s
R
R
R
R
R
R
R/W
R
R/W
R
R/W
R
R/W
R
R
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
…Continued
Rev. 1 — 17 March 2006
Description
Always 0.
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
Number of records/messages output from buffer 1.
Cleared to zero when FGPO_BASE1 register is written to.
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
Number of records/messages output from buffer 2.
Cleared to zero when FGPO_BASE1 register is written to.
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
THRESH1_REACHED interrupt generated when FGPO_NREC1
count equals this register value. Range: 1 to 2
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
THRESH2_REACHED interrupt generated when FGPO_NREC2
count equals this register value. Range: 1 to 2
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
Clock delay after a record/message is output before the next record/
message is output. Range: 1 to 2
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
Clock delay after a buffer is output before the next buffer is output.
Range: 1 to 2
Holds timestamp when buffer 1 completed.
Holds timestamp when buffer 2 completed.
Chapter 13: FGPO: Fast General Purpose Output
24
-1
24
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
-1
PNX17xx Series
24
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