SC3200UFH-266F AMD (ADVANCED MICRO DEVICES), SC3200UFH-266F Datasheet - Page 225
SC3200UFH-266F
Manufacturer Part Number
SC3200UFH-266F
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.SC3200UFH-266F.pdf
(428 pages)
Specifications of SC3200UFH-266F
Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / Rohs Status
Compliant
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Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0
AMD Geode™ SC3200 Processor Data Book
Offset 28h-2Bh
31:1
Bit
4
3
2
1
0
0
Description
PME Edge/Level Select. Selects the type (edge or level) of the signal that issues a PME from the selected GPIO signal.
0: Edge input. (Default)
1: Level input.
For normal operation, always set this bit to 0 (edge input). Erratic system behavior results if this bit is set to 1.
See the note in the description of this register for more information about the default value of this bit.
Lock. This bit locks the selected GPIO signal. Once this bit is set to 1 by software, it can only be cleared to 0 by power on
reset or by WATCHDOG reset.
0: No effect. (Default)
1: Direction, output type, pull-up and output value locked.
Pull-Up Control. Enables/disables the internal pull-up capability of the selected GPIO signal. It supports open-drain output
signals with internal pull-ups and TTL input signals.
0: Disable.
1: Enable. (Default)
Bits [1:0] of this register must = 01 for this bit to have effect.
Output Type. Controls the output buffer type (open-drain or push-pull) of the selected GPIO signal.
0: Open-drain. (Default)
1: Push-pull.
Bit 0 of this register must be set to 1 for this bit to have effect.
Output Enable. Indicates the GPIO signal output state. It has no effect on input.
0: TRI-STATE - Setting for GPIO to function as an input only. (Default)
1: Output enabled.
Reserved. Must be set to 0.
GPIO Reset. Reset the GPIO logic.
0: Disable.
1: Enable.
Write 0 to clear.
This bit is level-sensitive and must be cleared after the reset is enabled (normal operation requires this bit to be 0).
Table 6-30. F0BAR0+I/O Offset: GPIO Configuration Registers (Continued)
GPIO Reset Control Register (R/W)
32581C
Reset Value: 00000000h
225
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