SC3200UFH-266F AMD (ADVANCED MICRO DEVICES), SC3200UFH-266F Datasheet - Page 23

• Manufacturer Part Number: SC3200UFH-266F
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC3200UFH-266F

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Compliant

Architecture Overview
• Sub-ISA: See Section 3.4.7 "Sub-ISA Interface Signals"
• GPIO: See Section 3.4.16 "GPIO Interface Signals" on
• More detailed information about each of these interfaces
• Super/IO Block Interfaces: See Section 4.2 "Multi-
The Core Logic module interface to the GX1 module con-
sists of seven miscellaneous connections, the PCI bus
interface signals, plus the display controller connections.
Note that the PC/AT legacy signals NMI, WM_RST, and
A20M are all virtual functions executed in SMM (System
Management Mode) by the BIOS.
• PSERIAL is a one-way serial bus from the GX1 to the
• IRQ13 is an input from the GX1 module indicating that a
• INTR is the level output from the integrated 8259A PICs
• SMI# is a level-sensitive interrupt to the GX1 module
• SUSP# and SUSPA# are handshake signals for imple-
• CPU_RST resets the CPU and is asserted for approxi-
• PCI bus interface signals.
2.4
The SuperI/O (SIO) module is a PC98 and ACPI compliant
SIO that offers a single-cell solution to the most commonly
used ISA peripherals.
AMD Geode™ SC3200 Processor Data Book
on page 57, Section 6.2.5 "Sub-ISA Bus Interface" on
page 145, and Section 4.2 "Multiplexing, Interrupt Selec-
tion, and Base Address Registers" on page 70
page 65.
is provided in Section 6.2 "Module Architecture" on page
140.
plexing, Interrupt Selection, and Base Address Regis-
ters" on page 70, Section 3.4.5 "ACCESS.bus Interface
Signals" on page 52, Section 3.4.13 "Fast Infrared (IR)
Port Interface Signals" on page 62, and Section 3.4.12
"Parallel Port Interface Signals" on page 61.
Core Logic module used to communicate power-
management states and VSYNC information for VGA
emulation.
floating point error was detected and that INTR should
be asserted.
and is asserted if an unmasked interrupt request (IRQn)
is sampled active.
that can be configured to assert on a number of different
system events. After an SMI# assertion, SMM is entered
and program execution begins at the base of the SMM
address space. Once asserted, SMI# remains active
until the SMI source is cleared.
menting CPU Clock Stop and clock throttling.
mately 100 µs after the negation of POR#.
Super I/O Module
The SIO module incorporates: two Serial Ports, an Infrared
Communication Port that supports FIR, MIR, HP-SIR,
Sharp-IR, and Consumer Electronics-IR, a full IEEE 1284
Parallel Port, two ACCESS.bus Interface (ACB) ports, Sys-
tem Wakeup Control (SWC), and a Real-Time Clock (RTC)
that provides RTC timekeeping.
2.5
In addition to the four main modules (i.e., GX1, Core Logic,
Video Processor and SIO) that make up the SC3200, the
following blocks of logic have also been integrated into the
SC3200:
• Clock Generators as described in Section 4.5 "Clock
• Configuration Registers as described in Section 4.2
• A WATCHDOG timer as described in Section 4.3
• A High-Resolution timer as described in Section 4.4
2.5.1
This section provides a description of the reset flow of the
SC3200.
2.5.1.1
Power-on reset is triggered by assertion of the POR# sig-
nal. Upon power-on reset, the following things happen:
• Strap balls are sampled.
• PLL4, PLL5, and PLL6 are reset, disabling their output.
• Certain WATCHDOG and High-Resolution Timer
2.5.1.2
System reset causes signal PCIRST# to be issued, thus
triggering a reset of all PCI and LPC agents. A system
reset is triggered by any of the following events:
• Power-on, as indicated by POR# signal assertion.
• A WATCHDOG reset event (see Section 4.3.2
• Software initiated system reset.
Generators and PLLs" on page 81.
"Multiplexing, Interrupt Selection, and Base Address
Registers" on page 70.
"WATCHDOG" on page 77.
"High-Resolution Timer" on page 79.
When the POR# signal is negated, the clocks lock and
then each PLL outputs its clock. PLL6 is the last clock
generator to output a clock. See Section 4.5 "Clock
Generators and PLLs" on page 81.
register bits are cleared.
"WATCHDOG Registers" on page 78).
Clock, Timers, and Reset Logic
Reset Logic
Power-On Reset
System Reset
32581C
23