MT47H128M16HG-37E:A TR Micron Technology Inc, MT47H128M16HG-37E:A TR Datasheet - Page 12

MT47H128M16HG-37E:A TR

Manufacturer Part Number
MT47H128M16HG-37E:A TR
Description
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr
Datasheet

Specifications of MT47H128M16HG-37E:A TR

Organization
128Mx16
Address Bus
17b
Access Time (max)
500ps
Maximum Clock Rate
533MHz
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
0C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
195mA
Pin Count
84
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Functional Block Diagrams
Figure 3: Functional Block Diagram – 512 Meg x 4
PDF: 09005aef824f87b6
2gbddr2.pdf – Rev. E 06/10 EN
BA0–BA2
A0–A14,
RAS#
CAS#
ODT
WE#
CKE
CK#
CS#
CK
18
Address
register
registers
Mode
Control
logic
18
counter
Refresh
15
The DDR2 SDRAM is a high-speed CMOS, dynamic random access memory. It is inter-
nally configured as a multibank DRAM.
11
3
15
address
2
Row-
MUX
control
15
Bank
logic
Column-
counter/
address
latch
decoder
address
Bank 0
latch
row-
and
Bank 1
Bank 2
Bank 3
9
2
Bank 4
32,768
Bank 5
Bank 6
Bank 7
DM mask logic
(32,768 x 512 x 16)
I/O gating
Sense amplifiers
Memory array
Column
decoder
8,192
(x16)
512
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
12
Bank 7
COL0, COL1
CK, CK#
16
16
16
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Read
latch
CK out
drivers
Write
CK in
FIFO
and
4
4
4
4
Mask
Data
COL0, COL1
4
16
MUX
2Gb: x4, x8, x16 DDR2 SDRAM
generator
1
1
1
4
4
4
4
1
DQS
registers
Input
DATA
Functional Block Diagrams
4
DQS, DQS#
1
1
1
4
4
4
4
1
2
CK, CK#
4
1
DRVRS
2
DLL
RCVRS
© 2006 Micron Technology, Inc. All rights reserved.
sw1 sw2
sw1 sw2
sw1 sw2
sw1 sw2
R1
R1
R1
R1
R1
R1
ODT control
R2
R2
R2
R2
R2
R2
V
ss
Q
sw3
sw3
sw3
sw3
R3
R3
R3
R3
R3
R3
V
dd
Q
DQ0–DQ3
DQS, DQS#
DM

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