MT47H128M16HG-37E:A TR Micron Technology Inc, MT47H128M16HG-37E:A TR Datasheet - Page 31

MT47H128M16HG-37E:A TR

Manufacturer Part Number
MT47H128M16HG-37E:A TR
Description
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr
Datasheet

Specifications of MT47H128M16HG-37E:A TR

Organization
128Mx16
Address Bus
17b
Access Time (max)
500ps
Maximum Clock Rate
533MHz
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
0C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
195mA
Pin Count
84
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Table 11: DDR2 I
Notes 1–7 apply to the entire table
PDF: 09005aef824f87b6
2gbddr2.pdf – Rev. E 06/10 EN
Parameter/Condition
Operating one bank active-precharge
current:
t
MIN (I
valid commands; Address bus inputs are
switching; Data bus inputs are switching
Operating one bank active-read-pre-
charge current:
Iout = 0mA; BL = 4, CL = CL (I
=
(I
HIGH between valid commands; Address bus
inputs are switching; Data pattern is same as
I
Precharge power-down current: All banks
idle;
trol and address bus inputs are stable; Data
bus inputs are floating
Precharge quiet standby current: All
banks idle;
HIGH; Other control and address bus inputs
are stable; Data bus inputs are floating
Precharge standby current: All banks idle;
t
er control and address bus inputs are switch-
ing; Data bus inputs are switching
Active power-down current: All banks
open;
trol and address bus inputs are stable; Data
bus inputs are floating
Active standby current: All banks open;
t
t
valid commands; Other control and address
bus inputs are switching; Data bus inputs are
switching
Operating burst write current: All banks
open, continuous burst writes; BL = 4, CL =
CL (I
MAX (I
HIGH between valid commands; Address bus
inputs are switching; Data bus inputs are
switching
CK =
DD4W
CK =
CK =
RP (I
DD
t
CK (I
),
DD
t
DD
t
CK =
t
t
t
DD
RCD =
t
CK (I
CK (I
CK (I
), AL = 0;
DD
CK =
DD
); CKE is HIGH, CS# is HIGH between
); CKE is HIGH, CS# is HIGH between
),
),
t
DD
DD
DD
t
t
CK (I
t
RP =
RC =
CK =
t
t
CK (I
); CKE is HIGH, CS# is HIGH; Oth-
),
RCD (I
),
t
t
RC =
RAS =
DD
t
CK =
t
t
t
DD
RP (I
RC (I
CK (I
); CKE is LOW; Other con-
DD
DD
); CKE is LOW; Other con-
t
RC (I
DD
); CKE is HIGH, CS# is
t
DD
DD
t
CK (I
Specifications and Conditions (Die Revision C)
RAS MAX (I
); CKE is HIGH, CS# is
),
); CKE is HIGH, CS# is
DD
t
RAS =
DD
),
DD
),
t
RAS =
), AL = 0;
t
RAS =
t
RAS MIN
DD
),
t
RAS
t
t
RAS
RP =
t
CK
Symbol Configuration -187E -25E
I
I
I
I
I
I
I
DD4W
DD3Pf
DD3Ps
I
I
DD2Q
DD2N
DD3N
DD2P
DD0
DD1
Slow PDN exit
Fast PDN exit
MR[12] = 0
MR[12] = 1
x4, x8, x16
31
x4, x8
x4, x8
x4, x8
x4, x8
x4, x8
x4, x8
Electrical Specifications – I
x16
x16
x16
x16
x16
x16
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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2Gb: x4, x8, x16 DDR2 SDRAM
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-25
© 2006 Micron Technology, Inc. All rights reserved.
-3E/
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-3
DD
-37E
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Parameters
-5E
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Units
mA
mA
mA
mA
mA
mA
mA
mA

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