PNX1700EH NXP Semiconductors, PNX1700EH Datasheet - Page 235
PNX1700EH
Manufacturer Part Number
PNX1700EH
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1700EH.pdf
(832 pages)
Specifications of PNX1700EH
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / Rohs Status
Not Compliant
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Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
All IDE disk registers (eight command and one control) are accessible via PI. All IDE
disk registers are indirectly accessed via GPXIO registers.
diagram of the IDE interface.
The IDE port is multiplexed with PCI, FLASH and Motorola interface pins. There are
two dedicated pins, IDE_ENABLE (in this example XIO_SEL[1]) and INTREQ. The
IDE Disk interrupt (INTREQ) is connected to a GPIO signal, which is routed to the
VIC through GPIO or any direct interrupt line.
The PNX17xx Series SYS_RSTN_OUT can be connected with the IDE interface
reset. All outputs are driven on PCI_CLK. All inputs are registered on PCI_CLK. The
Low and High periods of DIOR/DIOW are programmable (using sel profile register).
All physical signals need to be isolated from PCI on the board as shown in
Figure 11: IDE Interface
PNX17xx
Rev. 1 — 17 March 2006
PCI AD[31:16] - DD[15:0]
XIO_SEL[1] - IDE_ENABLE
PCI_AD0 - IORDY
Outputs
INTREQ
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Chapter 7: PCI-XIO Module
PNX17xx Series
Figure 11
IDE Cable
shows a block
Figure 12
7-14
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