PNX1700EH NXP Semiconductors, PNX1700EH Datasheet - Page 790
PNX1700EH
Manufacturer Part Number
PNX1700EH
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1700EH.pdf
(832 pages)
Specifications of PNX1700EH
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / Rohs Status
Not Compliant
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Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
1.1.3 Peripheral Module Wakeup Sequence
1.1.4 TM5250 Powerdown Modes
Remark: This bit does NOT gate the internal module clock or other clocks as clock
gating is not allowed inside a module.
Waking up a module is also under CPU control and is the reverse sequence to
powerdown:
The TM5250 CPU has two modes: Partial Powerdown and Full Powerdown.
Partial Powerdown Mode
The TM5250 CPU enters partial powerdown mode by performing a 'store' to a
specific MMIO address (the POWERDOWN register). The TM5250 then finishes any
pending transactions and go into a partial powerdown. In partial powerdown mode,
cycle counters, timers and interrupt logic in the TM5250 are still active. The TM5250
CPU wakes up from partial powerdown when an interrupt occurs or there is an
access to its MMIO space. This commonly used by the idle task in an operating
system.
Full Powerdown Mode
The TM5250 also have an externally-initiated full power shutdown mode i.e., no
wakeups when an interrupt occurs. Entering this mode is requested by asserting an
input signal to the TM5250. When this signal is asserted, the TM5250 finishes
pending transactions and gates-off its core clock.
•
•
•
•
•
•
•
•
The CPU writes/sets the device's POWERDOWN control bit (usually bit 31 of
offset 0xFF4). Setting this bit causes the device to power down elements such as
memories and register files.
After setting the powerdown bit, none of the device's registers is accessible,
except the one containing the POWERDOWN bit, which is 100% operational.
–
–
The CPU programs the Clock module to stop/slow down the clock signals. This
assures the Clock module is stopped in a controlled way (no glitches/illegal
periods).
At this point, the register with the POWERDOWN bit is still the only accessible
register and the block is fully powered down.
Program the Clock module so that all related clock sources are set to their normal
operational frequencies.
Reset the POWERDOWN bit in the module.
Set up the module's configuration registers if needed.
Enable the module.
Reads from any other register do not hang.
Writes to any register (except the POWERDOWN bit register) are completed
fully or result in an error.
Rev. 1 — 17 March 2006
Chapter 27: Power Management
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
27-2
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