SI3018-F-FSR Silicon Laboratories Inc, SI3018-F-FSR Datasheet - Page 62
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SI3018-F-FSR
Manufacturer Part Number
SI3018-F-FSR
Description
Modem Chip Chipset 16-Pin SOIC T/R
Manufacturer
Silicon Laboratories Inc
Datasheet
1.SI3018-F-FSR.pdf
(112 pages)
Specifications of SI3018-F-FSR
Package
16SOIC
Main Category
Chipset
Sub-category
Data/Voice
Typical Operating Supply Voltage
3.3 V
Power Supply Type
Digital
Typical Supply Current
8.5 mA
Minimum Operating Supply Voltage
3 V
Maximum Operating Supply Voltage
3.6 V
Data Rate
54.6875Kbps
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
16
Mounting
Surface Mount
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI3018-F-FSR
Manufacturer:
SiliconL
Quantity:
52 026
Company:
Part Number:
SI3018-F-FSR
Manufacturer:
SILICON
Quantity:
57
Part Number:
SI3018-F-FSR
Manufacturer:
SILICONLABS/芯科
Quantity:
20 000
Si3050 + Si3018/19
Register 3. Interrupt Mask
Reset settings = 0000_0000
62
Bit
7
6
5
4
3
2
1
0
Name
Type
Bit
LCSOM
DODM
RDTM
ROVM
TGDM
FDTM
BTDM
POLM
Name
RDTM
R/W
D7
Ring Detect Mask.
0 = A ring signal does not cause an interrupt on the AOUT/INT pin.
1 = A ring signal causes an interrupt on the AOUT/INT pin.
Receive Overload Mask.
0 = A receive overload does not cause an interrupt on the AOUT/INT pin.
1 = A receive overload causes an interrupt on the AOUT/INT pin.
Frame Detect Mask.
0 = The ISOcap losing frame lock does not cause an interrupt on the AOUT/INT pin.
1 = The ISOcap losing frame lock causes an interrupt on the AOUT/INT pin.
Billing Tone Detect Mask.
0 = A detected billing tone does not cause an interrupt on the AOUT/INT pin.
1 = A detected billing tone causes an interrupt on the AOUT/INT pin.
Drop Out Detect Mask.
0 = A line supply dropout does not cause an interrupt on the AOUT/INT pin.
1 = A line supply dropout causes an interrupt on the AOUT/INT pin.
Loop Current Sense Overload Mask.
0 = An interrupt does not occur when the LCS bits are all 1s.
1 = An interrupt occurs when the LCS bits are all 1s.
TIP Ground Detect Mask.
0 = The TGD bit going active does not cause an interrupt on the AOUT/INT pin.
1 = The TGD bit going active causes an interrupt on the AOUT/INT pin.
Polarity Reversal Detect Mask (Si3019 line-side only).
This interrupt is generated from bit 7 of the LVS register. When this bit transitions, it indicates
that the polarity of TIP and RING is switched.
0 = A polarity change on TIP and RING does not cause an interrupt on the AOUT/INT pin.
1 = A polarity change on TIP and RING causes an interrupt on the AOUT/INT pin.
ROVM
R/W
D6
FDTM
R/W
D5
Rev. 1.31
BTDM
R/W
D4
Function
DODM
R/W
D3
LCSOM
R/W
D2
TGDM
R/W
D1
POLM
R/W
D0