MT41J256M8HX-15E IT:D Micron Technology Inc, MT41J256M8HX-15E IT:D Datasheet - Page 126

• Manufacturer Part Number: MT41J256M8HX-15E IT:D
• Description: MICMT41J256M8HX-15E_IT:D 2GB DDR3 SDRAM
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J256M8HX-15E IT:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: -40C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

Table 74: Write Leveling Matrix
Note 1 applies to the entire table
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
Leveling
Disabled
Enabled
MR1[7]
Write
(1)
Enabled (0)
MR1[12] MR1[3, 6, 9]
Disabled
Buffers
Output
(1)
Notes:
40Ω, 60Ω, or
40Ω, 60Ω, or
20Ω, 30Ω,
See normal operations
R
Value
When write leveling is enabled, the rising edge of DQS samples CK, and the prime DQ
outputs the sampled CK’s status. The prime DQ for a x4 or x8 configuration is DQ0 with
all other DQ (DQ[7:1]) driving LOW. The prime DQ for a x16 configuration is DQ0 for
the lower byte and DQ8 for the upper byte. It outputs the status of CK sampled by LDQS
and UDQS. All other DQ (DQ[7:1], DQ[15:9]) continue to drive LOW. Two prime DQ on
a x16 enable each byte lane to be leveled independently.
The write leveling mode register interacts with other mode registers to correctly config-
ure the write leveling functionality. Besides using MR1[7] to disable/enable write level-
ing, MR1[12] must be used to enable/disable the output buffers. The ODT value, burst
length, and so forth need to be selected as well. This interaction is shown in Table 74. It
should also be noted that when the outputs are enabled during write leveling mode, the
DQS buffers are set as inputs, and the DQ are set as outputs. Additionally, during write
leveling mode, only the DQS strobe terminations are activated and deactivated via the
ODT ball. The DQ remain disabled and are not affected by the ODT ball.
120Ω
120Ω
TT,nom
n/a
n/a
1. Expected usage if used during write leveling: Case 1 may be used when DRAM are on a
2. Since the DRAM DQS is not being driven (MR1[12] = 1), DQS ignores the input strobe,
3. Since the DRAM DQS is being driven (MR1[12] = 0), DQS captures the input strobe, and
dual-rank module and on the rank not being levelized or on any rank of a module not
being levelized on a multislotted system. Case 2 may be used when DRAM are on any
rank of a module not being levelized on a multislotted system. Case 3 is generally not
used. Case 4 is generally used when DRAM are on the rank that is being leveled.
and all R
only some R
ODT Ball
DRAM
High
High
Low
Low
TT,nom
TT,nom
values are allowed. This simulates a normal standby state to DQS.
DQS
Off
Off
On
On
values are allowed. This simulates a normal write state to DQS.
R
DRAM
TT,nom
DQ
Off
126
Prime DQ driving CK state: not terminated
Prime DQ driving CK state: not terminated
Other DQ driving LOW: not terminated
Other DQ driving LOW: not terminated
DQS not receiving: terminated by R
DQS not receiving: not terminated
Prime DQ High-Z: not terminated
Other DQ High-Z: not terminated
Prime DQ High-Z: not terminated
Other DQ High-Z: not terminated
DQS receiving: terminated by R
Micron Technology, Inc. reserves the right to change products or specifications without notice.
DQS receiving: not terminated
Write leveling not enabled
2Gb: x4, x8, x16 DDR3 SDRAM
DRAM State
© 2006 Micron Technology, Inc. All rights reserved.
TT
Write Leveling
TT
Case Notes
0
1
2
3
4
2
3