MT41J256M8HX-15E IT:D Micron Technology Inc, MT41J256M8HX-15E IT:D Datasheet - Page 133

• Manufacturer Part Number: MT41J256M8HX-15E IT:D
• Description: MICMT41J256M8HX-15E_IT:D 2GB DDR3 SDRAM
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J256M8HX-15E IT:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: -40C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

Figure 51: MRS to nonMRS Command Timing (
Mode Register 0 (MR0)
Burst Length
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
Notes:
Command
The base register, MR0, is used to define various DDR3 SDRAM modes of operation.
These definitions include the selection of a burst length, burst type, CAS latency, operat-
ing mode, DLL RESET, write recovery, and precharge power-down mode, as shown in
Figure 52 (page 134).
Burst length is defined by MR0[1: 0]. Read and write accesses to the DDR3 SDRAM are
burst-oriented, with the burst length being programmable to 4 (chop mode), 8 (fixed),
or selectable using A12 during a READ/WRITE command (on-the-fly). The burst length
determines the maximum number of column locations that can be accessed for a given
READ or WRITE command. When MR0[1:0] is set to 01 during a READ/WRITE com-
mand, if A12 = 0, then BC4 (chop) mode is selected. If A12 = 1, then BL8 mode is
selected. Specific timing diagrams, and turnaround between READ/WRITE, are shown
in the READ/WRITE sections of this document.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is reached. The block is
uniquely selected by A[i:2] when the burst length is set to 4 and by A[i:3] when the burst
length is set to 8 (where Ai is the most significant column address bit for a given config-
uration). The remaining (least significant) address bit(s) is (are) used to select the
Address
1. Prior to issuing the MRS command, all banks must be idle (they must be precharged,
2. Prior to Ta2 when
3. If R
4. CKE must be registered HIGH from the MRS command until
CKE
CK#
must be satisfied, and no data bursts can be in progress).
be issued.
fied prior to Ta1. ODT must also be registered LOW at each rising CK edge from T0 until
t
time power-down may occur (see Power-Down Mode (page 179)).
CK
MOD (MIN) is satisfied at Ta2.
TT
setting
Old
was previously enabled, ODT must be registered LOW at T0 so that ODTL is satis-
Valid
MRS
T0
t
MOD (MIN) is being satisfied, no commands (except NOP/DES) may
NOP
t
T1
MOD)
133
NOP
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T2
Updating setting
t MOD
2Gb: x4, x8, x16 DDR3 SDRAM
NOP
Ta0
Mode Register 0 (MR0)
Indicates A Break in
Time Scale
t
MRSPDEN (MIN), at which
© 2006 Micron Technology, Inc. All rights reserved.
NOP
Ta1
Don’t Care
Valid
Valid
MRS
non
Ta2
setting
New
t
RP