XC9536XV-7CS48C Xilinx Inc, XC9536XV-7CS48C Datasheet - Page 13

• Manufacturer Part Number: XC9536XV-7CS48C
• Description: IC CPLD 2.5V ISP 48-CSP
• Manufacturer: Xilinx Inc
• Series: XC9500XVr

Specifications of XC9536XV-7CS48C

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 2.37 V ~ 2.62 V
• Number Of Logic Elements/blocks: 2
• Number Of Macrocells: 36
• Number Of Gates: 800
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-CSBGA
• Voltage: 2.5V
• Memory Type: FLASH
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of I /o: -
• Number Of Logic Elements/cells: -

DS049 (v3.0) June 25, 2007
Product Specification
PIN
0
V
CCIO
1.2V
Voltage
Set to PIN
during valid user
operation
Output
0
R
Figure 13: Bus-Hold Logic
Standard
Figure 12: Output Slew-Rate Control For (a) Rising and (b) Falling Outputs
T
SLEW
Drive to
V
CCIO
(a)
Level
Slew-Rate Limited
R
BH
DS049_13_041400
I/O
www.xilinx.com
Time
Output Banking
XC95288XV and XC95144XV devices are designed with a
split-rail I/O structure. This permits the utilization of multiple
output drive levels for systems able to operate best in that
environment. The output partitioning is by function blocks
(FB). With this arrangement, designers can have some sets
of outputs driving to 2.5V and others set to 1.8V. Naturally, it
is possible to tie all rails to a single output voltage and get all
outputs driving to that level. Should designs be migrated
from one density to another in the same package, care
should be taken to remember the voltage assignments cho-
sen at the outset to assure consistency
Figure 14: Split Rail V
1.2V
Voltage
Output
V
CCIO1
0
XC95144XV and XC95288XV Devices
XC9500XV Family High-Performance CPLD
T
SLEW
Standard
Slew-Rate Limited
CC
V
GNDs
CCINTs
Output Power Connections in
(b)
(Figure
DS049_14_011501
DS049_12_041400
V
14).
CCIO2
Time
13