XC9536XV-7CS48C Xilinx Inc, XC9536XV-7CS48C Datasheet - Page 17

• Manufacturer Part Number: XC9536XV-7CS48C
• Description: IC CPLD 2.5V ISP 48-CSP
• Manufacturer: Xilinx Inc
• Series: XC9500XVr

Specifications of XC9536XV-7CS48C

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 2.37 V ~ 2.62 V
• Number Of Logic Elements/blocks: 2
• Number Of Macrocells: 36
• Number Of Gates: 800
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-CSBGA
• Voltage: 2.5V
• Memory Type: FLASH
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of I /o: -
• Number Of Logic Elements/cells: -

Power-Up Characteristics
The XC9500XV devices are well behaved under all operat-
ing conditions. During power-up each XC9500XV device
employs internal circuitry which keeps the device in the qui-
escent state until the V
(approximately 1.9V). During this time, all device pins and
JTAG pins are disabled and all device outputs are disabled
with the pins weakly pulled High, as shown in
When the supply voltage reaches a safe level, all user reg-
isters become initialized (typically within 300 μs), and the
device is immediately available for operation, as shown in
Figure
If the device is in the erased state (before any user pattern
is programmed), the device outputs remain disabled with
weak pull-up. The JTAG pins are enabled to allow the
device to be programmed at any time. All devices are
shipped in the erased state from the factory.
If the device is programmed, the device inputs and outputs
take on their configured states for normal operation. The
Table 5: XC9500XV Device Characteristics
DS049 (v3.0) June 25, 2007
Product Specification
IOB Bus-Hold
Device Outputs
Device Inputs and Clocks
Function Block
JTAG Controller
18.
R
Circuitry
Device
T
T
T
T
GCK
GSR
GTS
IN
CCINT
supply voltage is at a safe level
T
T
T
T
T
LOGILP
PTCK
PTSR
PTTS
LOGI
Quiescent
Figure 17: Detailed Timing Model
Disabled
Disabled
Disabled
Disabled
Pull-up
State
S*T
Table
www.xilinx.com
PTA
5.
D/T
EC
JTAG pins are enabled to allow device erasure or bound-
ary-scan tests at any time.
T
T
3.8 V
(Typ)
SUI
1.9V
(Typ)
0 V
HI
T
T
T
SR
T
PDI
AOI
RAI
Figure 18: Device Behavior During Power-up
F
Power
V
T
Macrocell
Erased Device
CCINT
No
COI
Q
Operation
Disabled
Disabled
Disabled
Enabled
Pull-up
XC9500XV Family High-Performance CPLD
Quiescent
State
T
OUT
Initialization of User Registers
User Operation
T
SLEW
As Configured
As Configured
As Configured
Valid User
Operation
Bus-Hold
Enabled
DS049_17_061200
Quiescent
State
T
DS049_18_061200
EN
Power
No
17