XC9536XV-7CS48C Xilinx Inc, XC9536XV-7CS48C Datasheet - Page 15

• Manufacturer Part Number: XC9536XV-7CS48C
• Description: IC CPLD 2.5V ISP 48-CSP
• Manufacturer: Xilinx Inc
• Series: XC9500XVr

Specifications of XC9536XV-7CS48C

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 2.37 V ~ 2.62 V
• Number Of Logic Elements/blocks: 2
• Number Of Macrocells: 36
• Number Of Gates: 800
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-CSBGA
• Voltage: 2.5V
• Memory Type: FLASH
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of I /o: -
• Number Of Logic Elements/cells: -

Design Security
XC9500XV devices incorporate advanced data security fea-
tures which fully protect the programming data against
unauthorized reading or inadvertent device erasure/repro-
gramming.
available.
The read security bits can be set by the user to prevent the
internal programming pattern from being read or copied.
When set, they also inhibit further program operations but
allow device erase. Erasing the entire device is the only way
to reset the read security bit.
The write security bits provide added protection against
accidental device erasure or reprogramming when the
JTAG pins are subject to noise, such as during system
power-up. Once set, the write-protection may be deacti-
vated when the device needs to be reprogrammed with a
valid pattern with a specific sequence of JTAG instructions
Table 3: Data Security Options
DS049 (v3.0) June 25, 2007
Product Specification
Default
Set
Table 3
R
shows the four different security settings
Program/Erase
Program/Erase
Read Allowed
Read Allowed
Allowed
Allowed
Default
Read Security
Program/Erase
Program/Erase
Read Inhibited
Read Inhibited
Inhibited
Inhibited
Set
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Low Power Mode
All XC9500XV devices offer a low-power mode for individ-
ual macrocells or across all macrocells. This feature allows
the device power to be significantly reduced.
Each individual macrocell may be programmed in
low-power mode by the user. Performance-critical parts of
the application can remain in standard power mode, while
other parts of the application may be programmed for
low-power operation to reduce the overall power dissipa-
tion. Macrocells programmed for low-power mode incur
additional delay (T
well as register setup time. Product term clock to output and
product term output enable delays are unaffected by the
macrocell power-setting.
Timing Model
The uniformity of the XC9500XV architecture allows a sim-
plified timing model for the entire device. The basic timing
model, shown in
that use the direct product terms only, with standard power
setting, and standard slew rate setting.
each of the key timing parameters is affected by the product
term allocator (if needed), low-power setting, and slew-lim-
ited setting.
The product term allocation time depends on the logic span
of the macrocell function, which is defined as one less than
the maximum number of allocators in the product term path.
If only direct product terms are used, then the logic span is
"0". The example in
terms are available with a span of "1". In the case of
Figure
Detailed timing information may be derived from the full tim-
ing model shown in
for each parameter are given in the individual device data
sheets.
7, the 18 product term function has a span of "2".
XC9500XV Family High-Performance CPLD
Figure
LP
Figure
Figure 6
) in pin-to-pin combinatorial delay as
16, is valid for macrocell functions
17. The values and explanations
shows that up to 15 product
Table 4
shows how
15