XC9536XV-7CS48C Xilinx Inc, XC9536XV-7CS48C Datasheet - Page 18

• Manufacturer Part Number: XC9536XV-7CS48C
• Description: IC CPLD 2.5V ISP 48-CSP
• Manufacturer: Xilinx Inc
• Series: XC9500XVr

Specifications of XC9536XV-7CS48C

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 2.37 V ~ 2.62 V
• Number Of Logic Elements/blocks: 2
• Number Of Macrocells: 36
• Number Of Gates: 800
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-CSBGA
• Voltage: 2.5V
• Memory Type: FLASH
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of I /o: -
• Number Of Logic Elements/cells: -

XC9500XV Family High-Performance CPLD
Power-Up Guidelines
Figure 19
tion controller, which transfers the EPROM bits to the
latches. Some important things to note are:
•
•
•
•
•
When V
The state machine cycles through addresses, delivers load
strobes to internal latches and completes the process by
enabling the I/O pins.
Figure 20
supply rises to its final value. At low voltage, the transistors
do not behave like transistors. As V
the transistors begin to wake up, but are not yet fully
functional. Above 1V, they can amplify and form basic
18
V
CCINT
V
The V
loading.
An internal clock source drives a state machine that
controls the overall process.
The bit loading process takes about 100 microseconds.
Internal configuration latches are automatically reset at
the beginning of the process.
The state machines, counters and strobes are built
from CMOS transistors, so they need voltage, setup
time, hold time, and propagation delay time to work
properly.
POR
CCINT
describes what happens inside the chip as the
shows a block diagram of the internal configura-
CCINT
Figure 19: Configuration Controller
passes a threshold, it automatically enables.
+
-
is sensed to determine when to begin the
Machine
Clock
State
CC
passes about a volt,
Strobes
Address
DS049_19_061200
www.xilinx.com
gates. Near 1.8V, they work correctly and can make reliable
latches. Above 2V, they can be reliably loaded with EPROM
bits. It is in this voltage neighborhood the POR circuits begin
transferring EPROM bits to the latches. XC9500XV POR
begins about 1.8V.
Development System Support
The XC9500XV family and associated in-system program-
ming capabilities are fully supported in either software solu-
tions available from Xilinx.
The Foundation Series is an all-in-one development system
containing schematic entry, HDL (VHDL, Verilog, and
ABEL), and simulation capabilities. It supports the
XC9500XV family as well as other CPLD and FPGA fami-
lies.
The Alliance Series includes CPLD and FPGA implementa-
tion technology as well as all necessary libraries and inter-
faces for Alliance partner EDA solutions.
The Xilinx WebPOWERED Software Solution offers design-
ers the flexibility to target the XC9500 and CoolRunner
Series CPLDs on the desktop with WebPACK. WebPACK
downloadable desktop solutions offer FREE CPLD software
modules for ABEL and HDL synthesis, device fitting and
JTAG programming.
V
POR
V
CC
0
Supply arrives at final value
Figure 20: Power-up Activity
Time
Configuration completes, part comes "alive"
Reset pulse delivered configuration begins
Logic alive, latches working
Transistors waking up
Inactive silicon, slight leakage
DS049 (v3.0) June 25, 2007
Product Specification
DS049_20_061200
®
R