ADSP-21371KSWZ-2B Analog Devices Inc, ADSP-21371KSWZ-2B Datasheet - Page 20

• Manufacturer Part Number: ADSP-21371KSWZ-2B
• Description: IC DSP 32BIT 266MHZ 208-LQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21371KSWZ-2B

• Package / Case: 208-LQFP
• Interface: DAI, DPI
• Operating Temperature: 0°C ~ 70°C
• Clock Rate: 266MHz
• Non-volatile Memory: ROM (512 kB)
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Mounting Type: Surface Mount
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 21371
• Core Frequency Typ: 266MHz
• Dsp Type: Floating Point
• Mmac: 532
• No. Of Pins: 208
• Interface Type: SPI, UART
• Rohs Compliant: Yes
• Operating Temperature Range: 0°C To +70°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21371
Clock Input
Table 14. Clock Input
1
2
3
Clock Signals
The ADSP-21371 can use an external clock or a crystal. See the
CLKIN pin description in
ure the ADSP-21371 to use its internal clock generator by
connecting the necessary components to CLKIN and XTAL.
Figure 6
operating in fundamental mode. Note that the clock rate is
achieved using a 16.67 MHz crystal and a PLL multiplier ratio
16:1 (CCLK:CLKIN achieves a clock speed of 266 MHz). To
achieve the full core clock rate, programs need to configure the
multiplier bits in the PMCTL register.
Parameter
Timing Requirements
t
t
t
t
t
Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.
Applies only for CLKCFG1–0 = 01 and default values for PLL control bits in PMCTL.
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t
CK
CKL
CKH
CKRF
CCLK
C1
22pF
CLKIN
R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL
DRIVE POWER. REFER TO CRYSTAL
MANUFACTURER’S SPECIFICATIONS
*TYPICAL VALUES
3
CLKIN
Figure 6. 266 MHz Operation (Fundamental Mode Crystal)
shows the component connections used for a crystal
16.67 MHz
R1
1M�*
Y1
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V to 2.0 V)
CCLK Period
ADSP-2137X
Figure 5. Clock Input
t
CKH
Table
XTAL
5. The programmer can config­
R2
47�*
C2
22pF
t
CK
t
CKL
Rev. 0 | Page 20 of 48 | June 2007
Min
22.5
10
10
3.75
1
1
1
1
CCLK
.
266 MHz
Max
320
180
180
6
10
2
2
2
Unit
ns
ns
ns
ns
ns