ADSP-21371KSWZ-2B Analog Devices Inc, ADSP-21371KSWZ-2B Datasheet - Page 40

• Manufacturer Part Number: ADSP-21371KSWZ-2B
• Description: IC DSP 32BIT 266MHZ 208-LQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21371KSWZ-2B

• Package / Case: 208-LQFP
• Interface: DAI, DPI
• Operating Temperature: 0°C ~ 70°C
• Clock Rate: 266MHz
• Non-volatile Memory: ROM (512 kB)
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Mounting Type: Surface Mount
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 21371
• Core Frequency Typ: 266MHz
• Dsp Type: Floating Point
• Mmac: 532
• No. Of Pins: 208
• Interface Type: SPI, UART
• Rohs Compliant: Yes
• Operating Temperature Range: 0°C To +70°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21371
SPI Interface—Slave
Table 38. SPI Interface Protocol
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
SPICLKS
SPICHS
SPICLS
SDSCO
HDS
SSPIDS
HSPIDS
SDPPW
DSOE
DSDHI
DDSPIDS
HDSPIDS
DSOV
CPHASE = 1
CPHASE = 0
(OUTPUT)
(OUTPUT)
(CP = 1)
SPICLK
(CP = 0)
(INPUT)
SPICLK
(INPUT)
MISO
MISO
(INPUT)
(INPUT)
(INPUT)
SPIDS
MOSI
MOSI
t
S D S C O
t
t
D S O E
D S O V
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPIDS Assertion to First SPICLK Edge
CPHASE = 0
CPHASE = 1
Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0
Data Input Valid to SPICLK edge (Data Input Set-up Time)
SPICLK Last Sampling Edge to Data Input Not Valid
SPIDS Deassertion Pulse Width (CPHASE=0)
SPIDS Assertion to Data Out Active
SPIDS Deassertion to Data High Impedance
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
SPIDS Assertion to Data Out Valid (CPHAS E = 0)
t
t
S P IC H S
S S P I D S
—
Slave Switching and Timing Specifications
MSB
t
t
D D S P I D S
MSB VALID
S P I C L S
MSB VALID
MSB
t
Rev. 0 | Page 40 of 48 | June 2007
D D S P I D S
Figure 30. SPI Slave Timing
t
t
S P I C H S
S P I C L S
t
S S P I D S
t
D D S P I D S
LSB VALID
t
t
S P I C L K S
S S P I D S
t
H D S P I D S
LSB
LSB VALID
t
H S P I D S
Min
4 × t
2 × t
2 × t
2 × t
2 × t
2 × t
2
2
2 × t
0
0
2 × t
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
t
H S P I D S
t
H D S
LSB
– 2
– 2
– 2
t
S D P P W
t
t
t
Max
6.8
6.8
9.5
5 × t
D S D H I
H D S P I D S
D S D H I
PCLK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns