DSPB56725AF Freescale Semiconductor, DSPB56725AF Datasheet - Page 36
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DSPB56725AF
Manufacturer Part Number
DSPB56725AF
Description
DSP 24BIT AUD 250MHZ 80-LQFP
Manufacturer
Freescale Semiconductor
Series
Symphony™r
Type
Audio Processorr
Specifications of DSPB56725AF
Interface
Host Interface, I²C, SAI, SPI
Clock Rate
250MHz
Non-volatile Memory
External
On-chip Ram
112kB
Voltage - I/o
3.30V
Voltage - Core
1.20V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
80-LQFP
Processor Series
DSP567xx
Core
56300
Leaded Process Compatible
Yes
Rohs Compliant
Yes
Peak Reflow Compatible (260 C)
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPB56725AF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Table 17
36
LCLK cycle time
Input setup to LCLK (except LGTA/LUPWAIT)
Input hold from LCLK (except LGTA/LUPWAIT)
LGTA valid time
LUPWAIT valid time
LALE negedge to LAD (address phase) invalid (address latch hold
time)
LALE valid time
Output setup from LCLK (except LAD[23:0] and LALE)
Output hold from LCLK (except LAD[23:0] and LALE)
LAD[23:0] output setup from LCLK
LAD[23:0] output hold from LCLK
LCLK to output high impedance for LAD[23:0]
Note: Negative hold time means the signal could be invalid before LCLK rising edge.
lists the EMC timing parameters with EMC PLL bypassed.
Table 17. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 4)
Symphony
Parameter
™
DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2
1
Symbol
T
T
T
T
T
T
T
T
T
T
upwait
T
ale_h
T
out_s
out_h
ad_h
ad_s
ad_z
in_s
in_h
ale
gta
clk
4 × T c
Min
–1
22
22
14
—
8
4
9
8
8
7
Freescale Semiconductor
Max
8.1
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns