ADSP-BF532SBB400 Analog Devices Inc, ADSP-BF532SBB400 Datasheet - Page 11

• Manufacturer Part Number: ADSP-BF532SBB400
• Description: IC DSP CTLR 16BIT 400MHZ 169-BGA
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF532SBB400

• Interface: SPI, SSP, UART
• Clock Rate: 400MHz
• Non-volatile Memory: ROM (1 kB)
• On-chip Ram: 84kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 169-BGA
• For Use With: ADZS-BF533-EZLITE - KIT W/BOARD EVAL FOR ADSP-BF533
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Silicon Anomaly List
15.
16.
DESCRIPTION:
If a MMR read immediately follows a stalled memory read, the MMR read will fail (i.e., the wrong data will be read).
Likewise, if a MMR write immediately follows a stalled memory read, the write may not take place (lost).
Instructions that include a memory read are:
and any of the above in parallel issue.
Instructions that include a memory write are:
and any of the above in parallel issue.
WORKAROUND:
Placing a NOP (or any non-memory access) in front of the MMR access will prevent this problem.
The VisualDSP++ Blackfin compiler includes a workaround for this hardware anomaly. The compiler will automatically enable the
workaround for the appropriate silicon revisions and part numbers, or the workaround can be enabled manually by specifying the
compiler flag ‘-workaround sdram-mmr-read'.
When enabled, the compiler will insert a NOP instruction between a load and an MMR load. It will insert the NOP instruction in cases
where the MMR load occurs with a constant address, e.g. *MMR_ADDR = value;. It cannot, however identify pointers unknown at compile
time (such as parameters to functions) as pointers to MMRs.
The macro __WORKAROUND_SDRAM_MMR_READ will be defined at compile, assemble and link stages when the workaround is enabled.
APPLIES TO REVISION(S):
0.3, 0.4
DESCRIPTION:
If the DMA Current Address register (DMAx_CURR_ADDR) of an active channel is read during the carry fix cycle, then the upper half of the
register will be off by one. The LSBs will have been updated with the new value, while the MSBs will still have the previous value. A
second read of the register will return the correct value.
The carry fix cycle occurs when the DMA address is being modified such that the address crosses a 64k boundary. If the DMA address
cannot cross a 64k address boundary, the read will never be incorrect.
WORKAROUND:
1) Avoid DMA addresses that cross a 64K address boundary.
OR
2) Read the DMA Current Address register twice to verify value read.
APPLIES TO REVISION(S):
0.3
05000198 - Failing MMR Accesses when Preceding Memory Read Stalls:
05000199 - Current DMA Address Shows Wrong Value During Carry Fix:
reg = [ Preg ], etc.
reg = [ Ireg ], etc.
stack pop, stack pop multiple
UNLINK
TESTSET
PREFETCH
[ Preg ] = reg, etc.
[ Ireg ] = reg, etc.
stack push, stack push multiple
LINK
NR003532D | Page 11 of 45 | July 2008
ADSP-BF531/BF532/BF533