ADSP-BF532SBB400 Analog Devices Inc, ADSP-BF532SBB400 Datasheet - Page 27

• Manufacturer Part Number: ADSP-BF532SBB400
• Description: IC DSP CTLR 16BIT 400MHZ 169-BGA
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF532SBB400

• Interface: SPI, SSP, UART
• Clock Rate: 400MHz
• Non-volatile Memory: ROM (1 kB)
• On-chip Ram: 84kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 169-BGA
• For Use With: ADZS-BF533-EZLITE - KIT W/BOARD EVAL FOR ADSP-BF533
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Silicon Anomaly List
48.
DESCRIPTION:
If a SSYNC, CSYNC, or IDLE is placed in the second to last instruction of a hardware loop, there is a possibility that the processor will enter
an infinite stall when trying to execute the sync.
WORKAROUND:
Do not put a SSYNC, CSYNC, or IDLE instruction in the second to last instruction of a hardware loop.
Because an interrupt or an exception will bring the processor out of the stall, this problem may not be obvious if you're running DMA or
interrupts.
The VisualDSP++ Blackfin Compiler includes a workaround for this anomaly. The compiler will automatically enable the workaround for
the appropriate silicon revisions and part numbers, or you can enable the workaround manually by specifying the compiler flag ‘-
workaround pre-loop-end-sync-stall-264'.
With the workaround enabled, the compiler will ensure that the second to last instruction of a hardware loop is not a CSYNC, SSYNC or
IDLE instruction, which has the potential to trigger the anomaly.
The macro __WORKAROUND_PRE_LOOP_END_SYNC_STALL_264 will be defined at compile, assemble, and link build phases when the
workaround is enabled.
APPLIES TO REVISION(S):
0.3, 0.4
05000264 - CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop:
NR003532D | Page 27 of 45 | July 2008
ADSP-BF531/BF532/BF533