ADSP-BF532SBB400 Analog Devices Inc, ADSP-BF532SBB400 Datasheet - Page 5

• Manufacturer Part Number: ADSP-BF532SBB400
• Description: IC DSP CTLR 16BIT 400MHZ 169-BGA
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF532SBB400

• Interface: SPI, SSP, UART
• Clock Rate: 400MHz
• Non-volatile Memory: ROM (1 kB)
• On-chip Ram: 84kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 169-BGA
• For Use With: ADZS-BF533-EZLITE - KIT W/BOARD EVAL FOR ADSP-BF533
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Silicon Anomaly List
2.
05000099 - UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time:
DESCRIPTION:
UART Line Status Register (UART_LSR) bits are not updated at the same time. Direct Polling of the UART_LSR register may miss any of the
Line Status conditions.
WORKAROUND:
When using polling mode. The SIC_ISR register should be polled to determine when it is safe to read UART_LSR, UART_RBR, and write
UART_THR. Below is a coding example for determining when received data is ready and determining if there was a receive error. The
UART_TX, UART_RX, and UART Error Interrupt are masked in SIC_IMASK for polling mode (no interrupt occurs).
APPLIES TO REVISION(S):
0.3, 0.4
#define IRQ_UART_RX 0x4000
#define IRQ_UART_ERROR 0x40
receive_polling:
data_ready:
p0.l = lo(UART_GCTL);
p0.h = hi(UART_GCTL);
p2.l = lo(SIC_ISR);
p2.h = hi(SIC_ISR);
r1 = PEN | WLS(8) (z);
w[p0+UART_LCR-UART_GCTL] = r1;
r1 = ERBFI | ELSI (z);
w[p0+UART_IER-UART_GCTL] = r1;
r2 = w[p2] (z);
CC = bittst (r2, bitpos (IRQ_UART_RX));
if !CC jump receive_polling;
csync;
r1 = w[p0+UART_LSR-UART_GCTL] (z);
r0 = w[p0+UART_RBR-UART_GCTL] (z);
CC = bittst (r2, bitpos (IRQ_UART_ERROR));
if CC jump error_handler;
[i0++] = r0;
jump receive_polling;
NR003532D | Page 5 of 45 | July 2008
ADSP-BF531/BF532/BF533