EP2C5F256C8N Altera, EP2C5F256C8N Datasheet - Page 137

IC CYCLONE II FPGA 5K 256-FBGA

EP2C5F256C8N

Manufacturer Part Number
EP2C5F256C8N
Description
IC CYCLONE II FPGA 5K 256-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet

Specifications of EP2C5F256C8N

Number Of Logic Elements/cells
4608
Number Of Labs/clbs
288
Total Ram Bits
119808
Number Of I /o
158
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
No. Of Logic Blocks
288
Family Type
Cyclone II
No. Of I/o's
158
I/o Supply Voltage
3.3V
Operating Frequency Max
320MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1656

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Altera Corporation
February 2008
LVTTL
2.5V
1.8V
1.5V
LVCMOS
SSTL_2_CLASS_I
SSTL_2_CLASS_II
SSTL_18_CLASS_I
SSTL_18_CLASS_II
1.5V_HSTL_CLASS_I
1.5V_HSTL_CLASS_II
1.8V_HSTL_CLASS_I
1.8V_HSTL_CLASS_II
PCI
PCI-X
DIFFERENTIAL_SSTL_2_
CLASS_I
DIFFERENTIAL_SSTL_2_
CLASS_II
Table 5–44. Maximum Input Clock Toggle Rate on Cyclone II Devices (Part 1 of 2)
I/O Standard
For example, the output toggle rate at 0 pF (default) load for SSTL-18
Class II 18mA I/O standard is 270 MHz on a
The derating factor is 29 ps/pF. For a 10pF load, the toggle rate is
calculated as:
Tables 5–44
devices.
= 1000 / (1000/toggle rate at default load + derating factor * load
value in pF/1000)
1000 / (1000/270 + 29 × 10/1000) = 250 (MHz)
Speed
Grade
450
450
450
300
450
500
500
500
500
500
500
500
500
500
500
–6
Column I/O Pins
Maximum Input Clock Toggle Rate on Cyclone II Devices (MHz)
through
Speed
Grade
405
405
405
270
405
500
500
500
500
500
500
500
500
500
500
–7
5–46
Speed
Grade
360
360
360
240
360
500
500
500
500
500
500
500
500
500
500
–8
show the I/O toggle rates for Cyclone II
DC Characteristics and Timing Specifications
Speed
Grade
500
500
500
500
450
450
450
300
450
500
500
500
500
350
350
500
500
–6
Row I/O Pins
Cyclone II Device Handbook, Volume 1
Speed
Grade
405
405
405
270
405
500
500
500
500
500
500
500
500
315
315
500
500
–7
Speed
Grade
500
500
500
500
360
360
360
240
360
500
500
500
500
280
280
500
500
–8
6 device column I/O pin.
Speed
Grade
420
450
450
300
420
500
500
500
500
500
500
500
500
350
350
500
500
–6
Dedicated Clock
Inputs
Speed
Grade
380
405
405
270
380
500
500
500
500
500
500
500
500
315
315
500
500
–7
Speed
Grade
340
360
360
240
340
500
500
500
500
500
500
500
500
280
280
500
500
5–47
–8

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