EP1C6T144C8 Altera, EP1C6T144C8 Datasheet - Page 57

• Manufacturer Part Number: EP1C6T144C8
• Description: IC CYCLONE FPGA 5980 LE 144-TQFP
• Manufacturer: Altera
• Series: Cyclone®r

Specifications of EP1C6T144C8

• Number Of Logic Elements/cells: 5980
• Number Of Labs/clbs: 598
• Total Ram Bits: 92160
• Number Of I /o: 98
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 144-TQFP, 144-VQFP
• Family Name: Cyclone®
• Number Of Logic Blocks/elements: 5980
• # I/os (max): 98
• Frequency (max): 275.03MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 5980
• Ram Bits: 92160
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1058

Altera Corporation
May 2008
Slew-Rate Control
The output buffer for each Cyclone device I/O pin has a programmable
output slew-rate control that can be configured for low noise or
high-speed performance. A faster slew rate provides high-speed
transitions for high-performance systems. However, these fast transitions
may introduce noise transients into the system. A slow slew rate reduces
system noise, but adds a nominal delay to rising and falling edges. Each
I/O pin has an individual slew-rate control, allowing the designer to
specify the slew rate on a pin-by-pin basis. The slew-rate control affects
both the rising and falling edges.
Bus Hold
Each Cyclone device I/O pin provides an optional bus-hold feature. The
bus-hold circuitry can hold the signal on an I/O pin at its last-driven
state. Since the bus-hold feature holds the last-driven state of the pin until
the next input signal is present, an external pull-up or pull-down resistor
is not necessary to hold a signal level when the bus is tri-stated.
The bus-hold circuitry also pulls undriven pins away from the input
threshold voltage where noise can cause unintended high-frequency
switching. The designer can select this feature individually for each I/O
pin. The bus-hold output will drive no higher than V
overdriving signals. If the bus-hold feature is enabled, the device cannot
use the programmable pull-up option. Disable the bus-hold feature when
the I/O pin is configured for differential signals.
The bus-hold circuitry uses a resistor with a nominal resistance (RBH) of
approximately 7 kΩ to pull the signal level to the last-driven state.
Table 4–15 on page 4–6
V
used to identify the next-driven input level.
The bus-hold circuitry is only active after configuration. When going into
user mode, the bus-hold circuit captures the value on the pin present at
the end of configuration.
Programmable Pull-Up Resistor
Each Cyclone device I/O pin provides an optional programmable
pull-up resistor during user mode. If the designer enables this feature for
an I/O pin, the pull-up resistor (typically 25 kΩ) holds the output to the
V
optional programmable pull-up resistor.
CCIO
CCIO
level of the output pin's bank. Dedicated clock pins do not have the
voltage level driven through this resistor and overdrive current
gives the specific sustaining current for each
CCIO
to prevent
I/O Structure
Preliminary
2–51