EP2C35F672C8N Altera, EP2C35F672C8N Datasheet - Page 108
![IC CYCLONE II FPGA 33K 672-FBGA](/photos/6/72/67268/ep2c35f672c8n_sml.jpg)
EP2C35F672C8N
Manufacturer Part Number
EP2C35F672C8N
Description
IC CYCLONE II FPGA 33K 672-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C35F672C8N
Number Of Logic Elements/cells
33216
Number Of Labs/clbs
2076
Total Ram Bits
483840
Number Of I /o
475
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
No. Of Logic Blocks
2076
Family Type
Cyclone II
No. Of I/o's
475
I/o Supply Voltage
3.3V
Operating Frequency Max
320MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
NANO-CYCLONE - KIT NANOBOARD AND CYCLONEII DC807-1002 - DAUGHTER CARD ALTERA CYCLONE IIP0301 - DE2 CALL FOR ACADEMIC PRICING544-1733 - PCI KIT W/CYCLONE II EP2C35N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1692
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C35F672C8N
Manufacturer:
YAGEO
Quantity:
500 000
Company:
Part Number:
EP2C35F672C8N
Manufacturer:
ALTERA
Quantity:
500
Part Number:
EP2C35F672C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Timing Specifications
5–18
Cyclone II Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Larger
Designs
TSU
TH
TCO
TCLR
Table 5–15. Cyclone II Performance (Part 4 of 4)
Table 5–16. LE_FF Internal Timing Microparameters (Part 1 of 2)
Parameter
This application uses registered inputs and outputs.
This application uses registered multiplier input and output stages within the DSP block.
This application uses the same clock source for both A and B ports.
This application uses independent clock sources for A and B ports.
This application uses PLL clock outputs that are globally routed to connect and drive M4K clock ports. Use of
non-PLL clock sources or local routing to drive M4K clock ports may result in lower performance numbers than
shown here. Refer to the Quartus II timing report for actual performance numbers.
These numbers are for commercial devices.
These numbers are for automotive devices.
Table 5–15
8-bit, 1024 pt, Quad Output,
4 Parallel FFT Engines, Buffered
Burst, 3 Mults/5 Adders FFT
function
8-bit, 1024 pt, Quad Output,
4 Parallel FFT Engines, Buffered
Burst, 4 Mults/2 Adders FFT
function
Applications
:
–6 Speed Grade
Min
–36
266
141
191
—
—
—
—
Internal Timing
Refer to
Max
250
Tables 5–16
—
—
—
—
—
—
—
(1)
8053
7453
LEs
Resources Used
–7 Speed Grade
Min
through
–40
–38
306
286
135
141
244
217
Memory
Blocks
M4K
60
60
5–19
Blocks
Max
DSP
277
36
48
—
—
—
—
—
—
—
for the internal timing parameters.
(2)
Speed
Grade
200.0
200.0
–6
–8 Speed Grade
Min
–40
–40
306
306
135
141
244
244
Performance (MHz)
Speed
Grade
195.0
195.0
(6)
–7
Altera Corporation
149.23
151.28
Speed
Max
Grade
304
—
—
—
—
—
—
—
February 2008
(7)
–7
(3)
163.02
163.02
Speed
Grade
Unit
–8
ps
ps
ps
ps
ps
ps
ps
ps