EP2C35F672C8N Altera, EP2C35F672C8N Datasheet - Page 55
![IC CYCLONE II FPGA 33K 672-FBGA](/photos/6/72/67268/ep2c35f672c8n_sml.jpg)
EP2C35F672C8N
Manufacturer Part Number
EP2C35F672C8N
Description
IC CYCLONE II FPGA 33K 672-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C35F672C8N
Number Of Logic Elements/cells
33216
Number Of Labs/clbs
2076
Total Ram Bits
483840
Number Of I /o
475
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
No. Of Logic Blocks
2076
Family Type
Cyclone II
No. Of I/o's
475
I/o Supply Voltage
3.3V
Operating Frequency Max
320MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
NANO-CYCLONE - KIT NANOBOARD AND CYCLONEII DC807-1002 - DAUGHTER CARD ALTERA CYCLONE IIP0301 - DE2 CALL FOR ACADEMIC PRICING544-1733 - PCI KIT W/CYCLONE II EP2C35N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1692
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C35F672C8N
Manufacturer:
YAGEO
Quantity:
500 000
Company:
Part Number:
EP2C35F672C8N
Manufacturer:
ALTERA
Quantity:
500
Part Number:
EP2C35F672C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 2–25. Cyclone II IOE in Bidirectional I/O Configuration
Altera Corporation
February 2007
Interconect
Column
or Row
io_clk[5..0]
data_in1
data_in0
Chip-Wide Reset
OE
clkout
aclr/prn
ce_in
ce_out
clkin
sclr/preset
The Cyclone II device IOE includes programmable delays to ensure zero
hold times, minimize setup times, or increase clock to output times.
A path in which a pin directly drives a register may require a
programmable delay to ensure zero hold time, whereas a path in which a
pin drives a register through combinational logic may not require the
delay. Programmable delays decrease input-pin-to-logic-array and IOE
input register delays. The Quartus II Compiler can program these delays
to automatically minimize setup time while providing a zero hold time.
Output Register
Input Register
OE Register
D
D
D
CLRN
CLRN
CLRN
PRN
ENA
PRN
ENA
PRN
ENA
Q
Q
Q
Pin Delay
Open-Drain Output
Output
Cyclone II Device Handbook, Volume 1
Input Register Delay
Logic Array Delay
or Input Pin to
Input Pin to
Cyclone II Architecture
V
CCIO
V
CCIO
Optional
PCI Clamp
Programmable
Pull-Up
Resistor
Bus Hold
2–43