EP2C35F672C8N Altera, EP2C35F672C8N Datasheet - Page 99
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EP2C35F672C8N
Manufacturer Part Number
EP2C35F672C8N
Description
IC CYCLONE II FPGA 33K 672-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C35F672C8N
Number Of Logic Elements/cells
33216
Number Of Labs/clbs
2076
Total Ram Bits
483840
Number Of I /o
475
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
No. Of Logic Blocks
2076
Family Type
Cyclone II
No. Of I/o's
475
I/o Supply Voltage
3.3V
Operating Frequency Max
320MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
NANO-CYCLONE - KIT NANOBOARD AND CYCLONEII DC807-1002 - DAUGHTER CARD ALTERA CYCLONE IIP0301 - DE2 CALL FOR ACADEMIC PRICING544-1733 - PCI KIT W/CYCLONE II EP2C35N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1692
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C35F672C8N
Manufacturer:
YAGEO
Quantity:
500 000
Company:
Part Number:
EP2C35F672C8N
Manufacturer:
ALTERA
Quantity:
500
Part Number:
EP2C35F672C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
February 2008
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
LVDS
Mini-LVDS
(2)
RSDS
LVPECL
(3) (6)
Differential
1.5-V HSTL
class I
and II
Differential
1.8-V HSTL
class I
and II
Differential
SSTL-2
class I
and II
Differential
SSTL-18
class I
and II
Table 5–8. Recommended Operating Conditions for User I/O Pins Using Differential Signal I/O Standards
Standard
I/O
Refer to the
measurement conditions on V
The RSDS and mini-LVDS I/O standards are only supported on output pins.
The LVPECL I/O standard is only supported on clock input pins. This I/O standard is not supported on output
pins.
The differential 1.8-V and 1.5-V HSTL I/O standards are only supported on clock input pins and PLL output clock
pins.
The differential SSTL-18 and SSTL-2 I/O standards are only supported on clock input pins and PLL output clock
pins.
The LVPECL clock inputs are powered by V
connect V
(4)
(4)
(5)
(5)
(2)
Table
2.375
2.375
2.375
3.135
1.425
2.375
CCIO
1.71
Min
5–8:
1.7
High-Speed Differential Interfaces in Cyclone II Devices
to typical value of 3.3V.
V
CCIO
Typ
2.5
2.5
2.5
3.3
1.5
1.8
2.5
1.8
(V)
2.625
2.625
2.625
3.465
1.575
2.625 0.36
Max
1.89
1.9
Table 5–8
pins with differential I/O standards.
ID
.
0.25
Min
0.1
0.1
0.2
—
—
—
V
shows the recommended operating conditions for user I/O
ID
Typ
0.6
—
—
—
—
—
—
—
(V)
CCINT
(1)
V
V
V
+ 0.6
+ 0.6
+ 0.6
Max
0.65
0.95
C C I O
C C I O
C C I O
—
—
—
and support all V
V
V
0.5 ×
– 0.2
0.5 ×
– 0.2
0.68
Min
C C I O
C C I O
0.1
—
—
—
—
DC Characteristics and Timing Specifications
chapter of the Cyclone II Device Handbook for
V
V
V
ICM
0.5 ×
0.5 ×
Typ
C C I O
C C I O
CCIO
—
—
—
—
—
—
Cyclone II Device Handbook, Volume 1
(V)
settings. However, it is recommended to
V
V
0.5 ×
+ 0.2
0.5 ×
+ 0.2
Max
C C I O
C C I O
2.0
0.9
—
—
—
—
Min
—
—
—
—
—
—
—
0
V
IL
(V)
– 0.20
– 0.20
– 0.35
– 0.25
V
V
V
V
Max
2.2
R E F
R E F
R E F
R E F
—
—
—
+ 0.20
+ 0.20
+ 0.35
+ 0.25
V
V
V
V
Min
2.1
—
—
—
R E F
R E F
R E F
R E F
V
IH
(V)
2.88
Max
—
—
—
—
—
—
—
5–9