EP2C35F672C8N Altera, EP2C35F672C8N Datasheet - Page 159
![IC CYCLONE II FPGA 33K 672-FBGA](/photos/6/72/67268/ep2c35f672c8n_sml.jpg)
EP2C35F672C8N
Manufacturer Part Number
EP2C35F672C8N
Description
IC CYCLONE II FPGA 33K 672-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C35F672C8N
Number Of Logic Elements/cells
33216
Number Of Labs/clbs
2076
Total Ram Bits
483840
Number Of I /o
475
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
No. Of Logic Blocks
2076
Family Type
Cyclone II
No. Of I/o's
475
I/o Supply Voltage
3.3V
Operating Frequency Max
320MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
NANO-CYCLONE - KIT NANOBOARD AND CYCLONEII DC807-1002 - DAUGHTER CARD ALTERA CYCLONE IIP0301 - DE2 CALL FOR ACADEMIC PRICING544-1733 - PCI KIT W/CYCLONE II EP2C35N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1692
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C35F672C8N
Manufacturer:
YAGEO
Quantity:
500 000
Company:
Part Number:
EP2C35F672C8N
Manufacturer:
ALTERA
Quantity:
500
Part Number:
EP2C35F672C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 5–10. DCD Measurement Technique for DDIO (Double-Data Rate) Outputs
Altera Corporation
February 2008
clk
INPUT
VCC
When an FPGA PLL generates the internal clock, the PLL output clocks
the IOE block. As the PLL only monitors the positive edge of the reference
clock input and internally re-creates the output clock signal, any DCD
present on the reference clock is filtered out. Therefore, the DCD for a
DDIO output with PLL in the clock path is better than the DCD for a
DDIO output without PLL in the clock path.
Tables 5–55
derivation for different I/O standards on Cyclone II devices. Examples
are also provided that show how to calculate DCD as a percentage.
LVCMOS
LVTTL
2.5-V
1.8-V
1.5-V
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
HSTL-15 Class I
HSTL-18 Class I
Table 5–55. Maximum DCD for Single Data Outputs (SDR) on Row I/O
Pins
Row I/O Output Standard
Notes
through
(1),
GND
V
CC
(2)
DFF
DFF
5–58
(Part 1 of 2)
D
D
CLRN
CLRN
PRN
PRN
give the maximum DCD in absolution
Q
Q
DC Characteristics and Timing Specifications
145
165
195
120
115
130
Cyclone II Device Handbook, Volume 1
C6
60
65
90
85
1
0
230
255
120
115
130
165
145
155
C7
90
75
230
255
135
175
135
165
205
155
output
C8
90
75
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
5–69