EP1K50FC484-3 Altera, EP1K50FC484-3 Datasheet - Page 29

• Manufacturer Part Number: EP1K50FC484-3
• Description: IC ACEX 1K FPGA 50K 484-FBGA
• Manufacturer: Altera
• Series: ACEX-1K®r

Specifications of EP1K50FC484-3

• Number Of Logic Elements/cells: 2880
• Number Of Labs/clbs: 360
• Total Ram Bits: 40960
• Number Of I /o: 249
• Number Of Gates: 199000
• Voltage - Supply: 2.375 V ~ 2.625 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 484-FBGA
• Family Name: ACEX™ 1K
• Number Of Usable Gates: 50000
• Number Of Logic Blocks/elements: 2880
• # I/os (max): 249
• Frequency (max): 166.67MHz
• Process Technology: CMOS
• Operating Supply Voltage (typ): 2.5V
• Logic Cells: 2880
• Ram Bits: 40960
• Device System Gates: 199000
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 544-1071

Altera Corporation
Figure 14. ACEX 1K Interconnect Resources
I/O Element (IOE)
Row
Interconnect
Column
Interconnect
IOE
IOE
IOE
IOE
LAB
LAB
B1
A1
I/O Element
An IOE contains a bidirectional I/O buffer and a register that can be used
either as an input register for external data that requires a fast setup time
or as an output register for data that requires fast clock-to-output
performance. In some cases, using an LE register for an input register will
result in a faster setup time than using an IOE register. IOEs can be used
as input, output, or bidirectional pins. The compiler uses the
programmable inversion option to invert signals from the row and
column interconnect automatically where appropriate. For bidirectional
registered I/O implementation, the output register should be in the IOE
and the data input and output enable registers should be LE registers
placed adjacent to the bidirectional pin.
I/O registers.
IOE
IOE
IOE
IOE
LAB
LAB
A2
B2
IOE
IOE
ACEX 1K Programmable Logic Device Family Data Sheet
IOE
IOE
LAB
LAB
A3
B3
IOE
IOE
IOE
IOE
Figure 15
See Figure 17
for details.
To LAB A5
To LAB A4
Carry Chains
Cascade &
To LAB B5
To LAB B4
shows the bidirectional
See Figure 16
for details.
IOE
IOE
IOE
IOE
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