EP1K50FC484-3 Altera, EP1K50FC484-3 Datasheet - Page 44

• Manufacturer Part Number: EP1K50FC484-3
• Description: IC ACEX 1K FPGA 50K 484-FBGA
• Manufacturer: Altera
• Series: ACEX-1K®r

Specifications of EP1K50FC484-3

• Number Of Logic Elements/cells: 2880
• Number Of Labs/clbs: 360
• Total Ram Bits: 40960
• Number Of I /o: 249
• Number Of Gates: 199000
• Voltage - Supply: 2.375 V ~ 2.625 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 484-FBGA
• Family Name: ACEX™ 1K
• Number Of Usable Gates: 50000
• Number Of Logic Blocks/elements: 2880
• # I/os (max): 249
• Frequency (max): 166.67MHz
• Process Technology: CMOS
• Operating Supply Voltage (typ): 2.5V
• Logic Cells: 2880
• Ram Bits: 40960
• Device System Gates: 199000
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 544-1071

ACEX 1K Programmable Logic Device Family Data Sheet
Figure 20. ACEX 1K JTAG Waveforms
44
Captured
Driven
Signal
Signal
to Be
to Be
TMS
TDO
TCK
TDI
Table 17
t
t
t
t
t
t
t
t
t
t
t
t
t
t
JCH
Symbol
JCP
JCH
JCL
JPSU
JPH
JPCO
JPZX
JPXZ
JSSU
JSH
JSCO
JSZX
JSXZ
Table 17. ACEX 1K JTAG Timing Parameters & Values
t
t
JPZX
JSZX
t
JCP
t
JSSU
shows the timing parameters and values for ACEX 1K devices.
t
JCL
TCK clock period
TCK clock high time
TCK clock low time
JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
t
JSH
t
t
JPCO
JSCO
t
JPSU
Parameter
t
t
JSXZ
JPH
t
JPXZ
Altera Corporation
Min
100
20
45
50
50
20
45
Max
25
25
25
35
35
35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns