XC4013-6PQ240C Xilinx Inc, XC4013-6PQ240C Datasheet
XC4013-6PQ240C
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XC4013-6PQ240C Summary of contents
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... Max RAM Bits 2,048 3,200 Number of IOBs 64 80 *XC4010D and XC4013D have no RAM XC4000, XC4000A, XC4000H Logic Cell Array Families Product Description Description The XC4000 families of Field-Programmable Gate Arrays (FPGAs) provide the benefits of custom CMOS VLSI, while avoiding the initial cost, time delay, and inherent risk of a conventional masked gate array ...
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XC4000, XC4000A, XC4000H Logic Cell Array Families XC4000 Compared to XC3000A For those readers already familiar with the XC3000A family of Xilinx Field Programmable Gate Arrays, here is a concise list of the major new features in the XC4000 family. ...
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Architectural Overview The XC4000 families achieve high speed through ad- vanced semiconductor technology and through improved architecture, and supports system clock rates MHz. Compared to older Xilinx FPGA families, the XC4000 families are more powerful, offering ...
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XC4000, XC4000A, XC4000H Logic Cell Array Families G4 G3 LOGIC FUNCTION G' OF G1- LOGIC FUNCTION OF F', G', AND LOGIC FUNCTION F' OF F1- (CLOCK) Figure 1. Simplified Block Diagram of ...
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Speed Is Enhanced Two Ways Delays in LCA-based designs are layout dependent. While this makes it hard to predict a worst-case guaranteed performance, there is a rule of thumb designers can consider — the system clock rate should not exceed ...
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... Each of these wired-AND gates is capable of accepting inputs on the XC4005 and 72 on the XC4013. These decoders may also be split in two when a large number of narrower decoders are required for a maximum of 32 per device. These dedicated decod- ers accept I/O signals and internal signals as inputs and generate a decoded internal signal in 18 ns, pin-to-pin ...
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In the XC4000 families, these constraints have been largely eliminated. This makes it easier for the software to com- plete the routing of complex interconnect patterns. Chip architects and software ...
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XC4000, XC4000A, XC4000H Logic Cell Array Families pass through a global buffer before arriving at the IOB. This eliminates the possibility of a data hold-time requirement at the external pin. The I1 and I2 signals that exit the block can ...
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CLB in the array. Each Switch Matrix consists of programmable n-channel pass transistors used to establish connections between the single-length lines (Figure 7). For example, a signal entering on the right side of the Switch Matrix can be ...
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XC4000, XC4000A, XC4000H Logic Cell Array Families Communication between Longlines and single-length lines is controlled by programmable interconnect points at the line intersections. Double-length lines do not connect to other lines. Three-State Buffers A pair of 3-state buffers, associated with ...
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I/O functions, latches, Boolean functions, RAM and ROM memory blocks, multiplexers, shift registers, and barrel shifters. Designing with macros is as easy as designing with standard SSI/MSI functions. The ‘soft macro’ library con- ...
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XC4000, XC4000A, XC4000H Logic Cell Array Families The XACT system also includes XDelay, a static timing analyzer. XDelay examines a design’s logic and timing to calculate the performance along signal paths, identify pos- sible race conditions, and detect set-up and ...
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Detailed Functional Description XC4000 and XC4000A Input/Output Blocks (For XC4000H family, see page 2-82) The IOB forms the interface between the internal logic and the I/O pads of the LCA device. Under configuration con- trol, the output buffer receives either ...
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XC4000, XC4000A, XC4000H Logic Cell Array Families The inputs drive TTL-compatible buffers with 1.2-V input threshold and a slight hysteresis of about 300 mV. These buffers drive the internal logic as well as the D-input of the input flip-flop. Under ...
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G4 G3 LOGIC FUNCTION G' OF G1- FUNCTION F4 F3 LOGIC FUNCTION F' OF F1- (CLOCK) Figure 13. Simplified Block Diagram of XC4000 Configurable Logic Block Carry Logic CIN ...
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XC4000, XC4000A, XC4000H Logic Cell Array Families Boundary Scan Boundary Scan is becoming an attractive feature that helps sophisticated systems manufacturers test their PC boards more safely and more efficiently. The XC4000 family implements IEEE 1149.1-compatible BYPASS, PRELOAD/SAMPLE and EXTEST ...
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IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB BYPASS REGISTER IOB INSTRUCTION REGISTER TDI M U TDO X INSTRUCTION REGISTER IOB BYPASS REGISTER IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB Figure 16. XC4000 Boundary Scan ...
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XC4000, XC4000A, XC4000H Logic Cell Array Families Interconnects The XC4000 families use a hierarchy of interconnect resources. • General purpose single-length and double-length lines offer fast routing between adjacent blocks, and highest flexibility for complex routes, but they incur a ...
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Oscillator An internal oscillator is used for clocking of the power-on time-out, configuration memory clearing, and as the source of CCLK in Master modes. This oscillator signal runs at a nominal 8 MHz and varies with process, V temperature between ...
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... The Header data, including the length count, is passed through and is captured by each LCA 2-26 HEADER PROGRAM DATA REPEATED FOR EACH LOGIC CELL ARRAY IN A DAISY CHAIN XC4008 XC4010/D XC4013/D XC4020 8,000 10,000 13,000 20,000 324 400 576 ...
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Boundary Scan >3.5 V Instructions Available: Yes Test M0 Generate One Time-Out Pulse Keep Clearing Configuration Memory EXTEST* SAMPLE/PRELOAD Completely Clear BYPASS Configuration Memory CONFIGURE* Once More (* if PROGRAM = High) ...
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XC4000, XC4000A, XC4000H Logic Cell Array Families tion data bits and a 4-bit frame error field frame data error is detected, the LCA device halts loading, and signals the error by pulling the open-drain INIT pin Low. After ...
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Length Count Match CCLK DONE I/O XC2000 Global Reset DONE XC3000 I/O Global Reset DONE I/O XC4000 CCLK_NOSYNC GSR Active DONE I/O XC4000 CCLK_SYNC GSR Active DONE I/O XC4000 UCLK_NOSYNC GSR Active DONE I/O XC4000 UCLK_SYNC GSR Active Synchronization Uncertainty ...
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XC4000, XC4000A, XC4000H Logic Cell Array Families Q3 Q1/Q4 STARTUP DONE FULL S Q LENGTH COUNT K CLEAR MEMORY CCLK 0 STARTUP.CLK 1 USER NET M * Figure 22. Start-up Logic All ...
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Reset Active Low Output 1 1 Active High Output etc . . . . the extra CCLK pulse. This solution requires one CLB, one IOB and pin, and an internal oscillator with ...
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XC4000, XC4000A, XC4000H Logic Cell Array Families Master Serial Mode GENERAL- PURPOSE USER I/O PINS PROGRAM In Master Serial mode, the CCLK output of the lead LCA device drives a Xilinx Serial PROM that feeds the LCA DIN input. Each ...
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A master device waits an additional Master Serial Mode Programming Switching Characteristics CCLK (Output DSCK Serial Data In ...
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XC4000, XC4000A, XC4000H Logic Cell Array Families Slave Serial Mode MICRO COMPUTER STRB D0 D1 I/O D2 PORT RESET In Slave Serial mode, an external signal drives the CCLK input(s) of the LCA device(s). The ...
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Slave Serial Mode Programming Switching Characteristics DIN 1 T DCC CCLK DOUT (Output) Description CCLK DIN setup DIN hold to DOUT High time Low time Frequency Note: Configuration must be delayed until the INIT of all daisy-chained LCA devices is ...
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XC4000, XC4000A, XC4000H Logic Cell Array Families Master Parallel Mode M0 DOUT HDC LDC GENERAL- PURPOSE RCLK RCLK USER I/O PINS INIT OTHER I/O PINS PROGRAM PROGRAM Master Parallel mode, the ...
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Using an open-collector or open-drain driver to hold INIT Low before the beginning of configuration, causes the LCA device to wait after having completed the configuration memory clear operation. When INIT is no longer held Low externally, the device determines ...
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XC4000, XC4000A, XC4000H Logic Cell Array Families Synchronous Peripheral Mode CLOCK DATA BUS CONTROL SIGNALS REPROGRAM Synchronous Peripheral mode can also be considered Slave Parallel mode. An external signal drives the CCLK input(s) of the LCA device(s). The first byte ...
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Synchronous Peripheral Mode Programming Switching Characteristics CCLK INIT BYTE 0 DOUT RDY/BUSY Description CCLK INIT (High) Setup time required D0-D7 Setup time required D0-D7 Hold time required CCLK High time CCLK Low time CCLK Frequency Notes: Peripheral Synchronous mode can ...
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XC4000, XC4000A, XC4000H Logic Cell Array Families Asynchronous Peripheral Mode DATA BUS +5 V ADDRESS BUS CONTROL SIGNALS REPROGRAM Write to LCA Asynchronous Peripheral mode uses the trailing edge of the logic AND condition of the CS0, CS1 and WS ...
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A Low on the PROGRAM input is the more radical ap- proach, and is recommended when the power-supply rise time is excessive or poorly defined. As long as PROGRAM is Low, the XC4000 device keeps clearing its configuration memory. When ...
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XC4000, XC4000A, XC4000H Logic Cell Array Families General LCA Switching Characteristics Vcc PROGRAM INIT CCLK OUTPUT or INPUT X1532 Master Modes Power-On-Reset M0 = High M0 = Low Program Latency CCLK (output) Delay period (slow) period (fast) Slave and Peripheral ...
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CONFIGURATION MODE: <M2:M1:M0> MASTER-SER SLAVE <0:0:0> <1:1:1> TDI TDI TCK TCK TMS TMS M1 (HIGH) (I) M1 (LOW) (I) M0 (HIGH) (I) M0 (LOW) (I) M2 (HIGH) (I) M2 (LOW) (I) HDC (HIGH) HDC (HIGH) LDC (LOW) LDC (LOW) INIT-ERROR ...
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XC4000, XC4000A, XC4000H Logic Cell Array Families Pin Descriptions Permanently Dedicated Pins V CC Eight or more (depending on package type) connections to the nominal +5 V supply voltage. All must be connected. GND Eight or more (depending on package ...
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HDC High During Configuration is driven High until configura- tion is completed available as a control output indicat- ing that configuration is not yet completed. After configu- ration, this is a user-programmable I/O pin. LDC Low During Configuration ...
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... CQFP PC84 PQ100 VQ100 CB100 PG120 TQ144 PG156 PQ160 CB164 PG191 CB196 PQ208 MQ208 PG223 BG225 PQ240 MQ240 PG299 HQ304 CODE - XC4003 - -10 XC4005 - XC4006 - XC4008 - -10 XC4010 - XC4010D - XC4013 - XC4013D - XC4020 - XC4025 - XC4002A - - XC4003A - XC4004A - XC4005A - XC4003H -6 -5 XC4005H - Commercial = MIL-STD-883C Class B ...